A method of manufacturing a semiconductor device includes bonding a first semiconductor die and a second semiconductor die to a first substrate, forming a conductive layer over the first semiconductor die, the second semiconductor die, and the first substrate, applying an encapsulant over the conductive layer, and removing a portion of the encapsulant, wherein the removing the portion of the encapsulant exposes the conductive layer.

A semiconductor device includes: an insulating layer; a circuit pattern on an upper surface of the insulating layer; a semiconductor element bonded to an upper surface of the circuit pattern through a first bonding material; an insulating component bonded to the upper surface of the circuit pattern through a second bonding material; and a lead electrode connecting the semiconductor element to the insulating component, wherein an upper surface of the semiconductor element is bonded to a lower surface of the lead electrode through a third bonding material, an upper surface of the insulating component is bonded to the lower surface of the lead electrode through a fourth bonding material, and the first bonding material, the second bonding material, the third bonding material, and the fourth bonding material are made of a same material.

A power semiconductor module includes an insulating substrate, a first conductive circuit pattern, a second conductive circuit pattern, a first semiconductor device, a second semiconductor device, a sealing member, and a first barrier layer. The sealing member seals the first semiconductor device, the second semiconductor device, the first conductive circuit pattern, and the second conductive circuit pattern. At least one of the first barrier layer and the sealing member includes a first stress relaxation portion. This configuration improves the reliability of the power semiconductor module.

An illumination apparatus comprises a plurality of LEDs aligned to an array of directional optical elements wherein the LEDs are substantially at the input aperture of respective optical elements. An electrode array is formed on the array of optical elements to provide at least a first electrical connection to the array of LED elements. Advantageously such an arrangement provides low cost and high efficiency from the directional LED array.

An illumination apparatus comprises a plurality of LEDs aligned to an array of directional optical elements wherein the LEDs are substantially at the input aperture of respective optical elements. An electrode array is formed on the array of optical elements to provide at least a first electrical connection to the array of LED elements. Advantageously such an arrangement provides low cost and high efficiency from the directional LED array.

Provided is a method of manufacturing a semiconductor having a double-sided substrate including preparing a first substrate on which a specific pattern is formed to enable electrical connection, preparing at least one semiconductor chip bonded to a metal post, bonding the at least one semiconductor chip to the first substrate, bonding a second substrate to the metal post, forming a package housing by packaging the first substrate and the second substrate to expose a lead frame, and forming terminal leads toward the outside of the package housing. Accordingly, the semiconductor chip and the metal post are previously joined to each other and are respectively bonded to the first substrate and the second substrate so that damage generated while bonding the semiconductor chip may be minimized and electrical properties and reliability of the semiconductor chip may be improved.

A package structure includes a first circuit board, a second circuit board, at least one electronic component, at least one conductive lead, and a molding compound. The first circuit board includes a first circuit layer and a second circuit layer. The second circuit board includes a third circuit layer and a fourth circuit layer. The electronic component is disposed between the first circuit board and the second circuit board. The conductive lead contacts at least one of the second circuit layer and the third circuit layer. The conductive lead has a vertical height, and the vertical height is greater than a vertical distance between the second circuit layer and the third circuit layer. The molding compound covers the first circuit board, the second circuit board, the electronic component, and the conductive lead. The molding compound exposes the first circuit layer and the fourth circuit layer, and the conductive lead extends outside the molding compound.

A semiconductor package includes: (1) a package substrate including an upper surface; (2) a semiconductor device disposed adjacent to the upper surface of the package substrate, the semiconductor device including an inactive surface; and (3) an antenna substrate disposed on the inactive surface of the semiconductor device.

A semiconductor package includes: (1) a package substrate including an upper surface; (2) a semiconductor device disposed adjacent to the upper surface of the package substrate, the semiconductor device including an inactive surface; and (3) an antenna substrate disposed on the inactive surface of the semiconductor device.

A peripheral nerve stimulator configured as a flexible circuit to stimulate or block the operation of a nerve or nerve bundle, including electrode array, cable and bond pad portions connected to an electronics package. The electrode array is configured for peripheral nerve modulation and may be curved cylindrically to encompass a nerve. A cylindrical curve can be imparted through thermoforming or by applying a stretchable polymer. The stretchable polymer places the electrode array portion into a cylinder when the electrode array portion is in a relaxed position. The electronics package includes low profile, stacked thin chip electronic components that are tunable in-situ, requiring less vertical and lateral space than stacked passives. The thin chip components may be high density trench capacitors, metal-on-semiconductor capacitors positioned on an integrated circuit chip. The thin chip components may include metal-insulator-metal capacitors having a tunable capacitance value and/or may be a binary capacitor array.