A method includes attaching a discrete component on a circuit board with a first glue, attaching an integrated circuit to the circuit board using a third glue, and attaching a cap to the circuit board using a second glue. The first glue has a composition such that it does not interact electrically with the second glue and does not interact electrically with the third glue.

Disclosed is a semiconductor package comprising a substrate, a semiconductor chip on the substrate, a molding layer on the substrate covering the semiconductor chip, and a shield layer on the molding layer. The shield layer includes a polymer in which a plurality of conductive structures and a plurality of nano-structures are distributed wherein at least some of the conductive structures are connected to one another.

A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.

The present application discloses a die sealant for chip packaging and a packaging structure, wherein epoxy resin adopted in the die sealant has flexible units such as polyether. In combination with the compounding of components such as a curing agent and a diluent, good flexibility and strength are achieved, and warpage is effectively reduced, wherein the warpage can be reduced to 0 mm, the modulus can reach up to 8 GPa or above, good silicon adhesion is achieved, and a silicon wafer can be effectively protected from bending cracks caused by warpage. Moreover, by adding a p-tert-butylphenol epoxy resin diluent, impacts of a monofunctional aliphatic diluent on a curing system can be further reduced effectively, and the flexibility and modulus of the die sealant can be further improved.

Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.

Stacked semiconductor die assemblies having memory dies stacked between partitioned logic dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a first logic die, a second logic die, and a thermally conductive casing defining an enclosure. The stack of memory dies can be disposed within the enclosure and between the first and second logic dies.

Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.

A semiconductor device includes a package substrate, a package component and at least one adhesive pattern. The package component has a thermal interface material (TIM) layer thereon. The adhesive pattern has a first surface facing the package substrate and a second surface opposite to the first surface, and the second surface of the at least one adhesive pattern is substantially coplanar with a surface of the TIM layer.

A packaged radio frequency (RF) module is disclosed. The module can include a substrate, a first die electrically and mechanically attached to the substrate, a second die electrically and mechanically attached to the substrate, an encapsulating material, and a lid attached to the substrate. The first die comprises a silicon-based die, such as an RF switch die, and the second die comprises a compound semiconductor die, such as an RF amplifier. The encapsulating material can protect electrical connections between the first die and the substrate. The substrate and the lid at least partially define an air cavity within which the first and the second die are mounted. An active surface of the second die is exposed to the air cavity.

A packaged radio frequency (RF) module is disclosed. The module can include a substrate, a first die electrically and mechanically attached to the substrate, a second die electrically and mechanically attached to the substrate, an encapsulating material, and a lid attached to the substrate. The first die comprises a silicon-based die, such as an RF switch die, and the second die comprises a compound semiconductor die, such as an RF amplifier. The encapsulating material can protect electrical connections between the first die and the substrate. The substrate and the lid at least partially define an air cavity within which the first and the second die are mounted. An active surface of the second die is exposed to the air cavity.