A semiconductor package may include: a chip stack including first to N.sup.th semiconductor chips stacked with an offset to one side such that edges thereof on the other side are exposed, and having first to N.sup.th chip pads disposed at the other-side edges, respectively; a bridge unit disposed adjacent to the other side of the chip stack and spaced apart from the chip stack; k.sup.th to N.sup.th wires extended in a vertical direction while one ends thereof are connected to the k.sup.th to N.sup.th chip pads among the first to Nth chip pads; first to (k−1).sup.th wires having one ends connected to the first to (k−1).sup.th chip pads among the first to N.sup.th chip pads; and an additional wire electrically coupled to the first to (k−1).sup.th wires, and extended in the vertical direction while one end thereof is connected to the bridge unit.

A package structure includes a substrate, a first electronic component, a second electronic component, a third electronic component and a connection component. The substrate includes a first surface and a second surface opposite the first surface. The first electronic component is disposed at the substrate and has a first active surface exposed from the second surface of the substrate. The second electronic component includes a second active surface facing the first active surface of the first electronic component. The second active surface of the second electronic component is electrically connected to the first active surface of the first electronic component. The third electronic component includes a third active surface facing the first active face of the first electronic component. The connection component electrically connects the third active surface of the third electronic component to the first active surface of the first electronic component. The connection component has at least two bendings.

A filament includes a plurality of strings including radiation-emitting semiconductor chips electrically connected in series; and a plurality of contact structures to contact the strings, wherein the contact structures electrically connect to semiconductor chips at ends of the strings such that the strings are electrically drivable via the contact structures, and the filament is configured such that the strings are electrically drivable at least separately from one another via the contact structures.

Implementations of semiconductor packages may include a die including a first side and a second side opposing the first side, the second side of the die coupled to a layer, a first end of a plurality of wires each bonded to the first side of the die, a mold compound encapsulating the die and the plurality of wires, and a second end of the plurality of wires each directly bonded to one of a plurality of bumps, wherein a surface of the layer is exposed through the mold compound.

A stack package includes a package substrate and a fan-out sub-package mounted on the package substrate using first and second connection bumps. The fan-out sub-package includes a first semiconductor die and redistributed line (RDL) patterns. Second semiconductor dies are stacked on the package substrate to provide a first step structure, and third semiconductor dies are stacked on the second semiconductor dies to provide a second step structure. The second and third semiconductor dies are connected to the package substrate by bonding wires.

Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

A floating die package including a cavity formed through sublimation of a sacrificial die encapsulant and sublimation or separation of die attach materials after molding assembly. A pinhole vent in the molding structure is provided as a sublimation path to allow gases to escape, whereby the die or die stack is released from the substrate and suspended in the cavity by the bond wires only.

A semiconductor device includes a semiconductor element, a conductive layer, terminals, and a sealing resin. The conductive layer, containing metal particles, is in contact with the reverse surface and the side surface of the semiconductor element. The terminals are spaced apart from and electrically connected to the semiconductor element. The sealing resin covers the semiconductor element. The conductive layer has an edge located outside of the semiconductor element as viewed in plan. Each terminal includes a top surface, a bottom surface, an inner side surface held in contact with the sealing resin, and the terminal is formed with a dent portion recessed from the bottom surface and the inner side surface. The conductive layer and the bottom surface of each terminal are exposed from a bottom surface of the sealing resin.

A substrate-less integrated electronic element module for a semiconductor package, comprising: at least two electronic elements, each of the at least two electronic elements having first electrical connectors; and a first molding compound encapsulating the at least two electronic elements, the first molding compound comprising a first planar surface and an opposing second planar surface of the integrated electronic element module, wherein each of the first electrical connectors is directly exposed on the first planar surface of the integrated electronic element module. Further, a semiconductor package including the integrated electronic element module and the method of fabricating the same is provided.

A semiconductor package may include: a chip stack including first to N.sup.th semiconductor chips stacked with an offset to one side such that edges thereof on the other side are exposed, and having first to N.sup.th chip pads disposed at the other-side edges, respectively; a bridge unit disposed adjacent to the other side of the chip stack and spaced apart from the chip stack; k.sup.th to N.sup.th wires extended in a vertical direction while one ends thereof are connected to the k.sup.th to N.sup.th chip pads among the first to Nth chip pads; first to (k1).sup.th wires having one ends connected to the first to (k1).sup.th chip pads among the first to N.sup.th chip pads; and an additional wire electrically coupled to the first to (k1).sup.th wires, and extended in the vertical direction while one end thereof is connected to the bridge unit.