A device structure, along with methods of forming such, are described. The device structure includes a structure, a first passivation layer disposed on the structure, a buffer layer disposed on the first passivation layer, a barrier layer disposed on a first portion of the buffer layer, a redistribution layer disposed over the barrier layer, an adhesion layer disposed on the barrier layer and on side surfaces of the redistribution layer, and a second passivation layer disposed on a second portion of the buffer layer. The second passivation layer is in contact with the barrier layer, the adhesion layer, and the redistribution layer.

A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.

A method of manufacturing a semiconductor structure includes providing a substrate and an interlayer dielectric (ILD) over the substrate; disposing a first dielectric layer over the ILD and the substrate; forming a conductive member surrounded by the first dielectric layer; disposing a second dielectric layer over the first dielectric layer and the conductive member; forming a capacitor over the second dielectric layer; disposing a third dielectric layer over the capacitor and the second dielectric layer; forming a conductive via extending through the second dielectric layer, the capacitor and the third dielectric layer; forming a conductive pad over the conductive via; and forming a conductive bump over the conductive pad, wherein the disposing of the third dielectric layer includes disposing an oxide layer over the capacitor and disposing a nitride layer over the capacitor.

Disclosed embodiments include die-edge level passive devices for integrated-circuit device packages that provide a low-loss path to active and passive devices, by minimizing inductive loops.

A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising multiple encapsulating layers and multiple signal distribution structures, and a method of manufacturing thereof.

The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.

A multi-layered battery separator for a lithium secondary battery includes a first layer of a dry processed membrane bonded to a second layer of a wet processed membrane. The first layer may be made of a polypropylene based resin. The second layer may be made of a polyethylene based resin. The separator may have more than two layers. The separator may have a ratio of TD/MD tensile strength in the range of about 1.5-3.0. The separator may have a thickness of about 35.0 microns or less. The separator may have a puncture strength of greater than about 630 gf. The separator may have a dielectric breakdown of at least about 2000V.

A peripheral nerve stimulator configured as a flexible circuit to stimulate or block the operation of a nerve or nerve bundle, including electrode array, cable and bond pad portions connected to an electronics package. The electrode array is configured for peripheral nerve modulation and may be curved cylindrically to encompass a nerve. A cylindrical curve can be imparted through thermoforming or by applying a stretchable polymer. The stretchable polymer places the electrode array portion into a cylinder when the electrode array portion is in a relaxed position. The electronics package includes low profile, stacked thin chip electronic components that are tunable in-situ, requiring less vertical and lateral space than stacked passives. The thin chip components may be high density trench capacitors, metal-on-semiconductor capacitors positioned on an integrated circuit chip. The thin chip components may include metal-insulator-metal capacitors having a tunable capacitance value and/or may be a binary capacitor array.

A semiconductor package includes a first die, a second die, an encapsulant, a first inductor and a second inductor. The second die is stacked on the first die along a first direction. The encapsulant encapsulates the second die over the first die. The first inductor is disposed in the encapsulant and has a first spiral structure, wherein the first spiral structure has a plurality of first coils around a first axis, and the first axis is substantially perpendicular to the first direction. The second inductor is disposed in the encapsulant and having a second spiral structure, wherein the first inductor and the second inductor are disposed at opposite sides of the second die.

In an embodiment, a structure includes: a processor device including logic devices; a first memory device directly face-to-face bonded to the processor device by metal-to-metal bonds and by dielectric-to-dielectric bonds; a first dielectric layer laterally surrounding the first memory device; a redistribution structure over the first dielectric layer and the first memory device, the redistribution structure including metallization patterns; and first conductive vias extending through the first dielectric layer, the first conductive vias connecting the metallization patterns of the redistribution structure to the processor device.