A copper paste for pressureless bonding is a copper paste for pressureless bonding, containing: metal particles; and a dispersion medium, in which the metal particles include sub-micro copper particles having a volume average particle diameter of greater than or equal to 0.01 μm and less than or equal to 0.8 μm, and micro copper particles having a volume average particle diameter of greater than or equal to 2.0 μm and less than or equal to 50 μm, and the dispersion medium contains a solvent having a boiling point of higher than or equal to 300° C., and a content of the solvent having a boiling point of higher than or equal to 300° C. is greater than or equal to 2 mass % on the basis of a total mass of the copper paste for pressureless bonding.

A method of forming a semiconductor structure is provided. A layout of a substrate is provided. The layout includes a surface having an inner region and an outer region surrounding the inner region. An under bump metallurgy (UBM) pad region within the outer region is defined. The UBM pad region is partitioned into a first zone and a second zone, wherein the first zone faces towards a center of the substrate, and the second zone faces away from the center of the substrate. The substrate is provided according to the layout, wherein the providing of the substrate includes forming a conductive via in the substrate. The conductive via is disposed outside the second zone and at least partially overlaps the first zone from a top view perspective. A UBM pad is formed over the conductive via and within the UBM pad region.

Semiconductor light emitting device includes: substrate including main and back surfaces, first and second side surfaces, and bottom and top surfaces, wherein main surface includes first to fourth sides; first main surface electrode on main surface and including first base portion contacting the sides of the main surface, and die pad connected to first base portion; second main surface electrode disposed on the main surface and including second base portion contacting first and third sides of the main surface, and wire pad connected to second base portion; semiconductor light emitting element including first electrode pad and mounted on die pad; wire connecting first electrode pad and wire pad; first insulating film covering portion between first base portion and die pad; second insulating film covering portion between second base portion and wire pad and having end portions contacting main surface; and light-transmitting sealing resin.

The present invention relates to a semiconductor device. The semiconductor device includes: a first main electrode provided on an active region; a second main electrode provided on an opposite side of the semiconductor substrate from the first main electrode; a protection film covering a terminal region; and a non-electrolytic plating layer provided on the first main electrode not covered by the protection film, the first main electrode includes a center electrode in a center part and an outer peripheral electrode provided along the center electrode to be separately from the center electrode, the protection film is provided to extend from the terminal region to an end edge portion of the outer peripheral electrode, the center electrode and the outer peripheral electrode include: a first metal layer; and a second metal layer provided on the first metal layer, and the outer peripheral electrode includes a hole part to reach the first metal layer.

A technique for marking semiconductor devices with an identifiable mark or alphanumeric text yields a high-contrast, easily distinguishable mark on an electrical terminal of the device without impacting the device's breakdown voltage capability and without compromising the solderability and wire bondability of the terminal. This approach deposits the mark on the terminal as a patterned layer of palladium, which offers good contrast with the base metal of the terminal and maintains the solderability and bondability of the terminal.

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a method of manufacturing a packaging device includes forming an interconnect wiring over a substrate, and forming conductive balls over portions of the interconnect wiring. A molding material is deposited over the conductive balls and the substrate, and a portion of the molding material is removed from over scribe line regions of the substrate.

A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.

Embodiments include forming a die, the die including a pad and a passivation layer over the pad. A via is formed to the pad through the passivation layer. A solder cap is formed on the via, where a first material of the solder cap flows to the sidewall of the via. In some embodiments, the via is encapsulated in a first encapsulant, where the first encapsulant is a polymer or molding compound selected to have a low co-efficient of thermal expansion and/or low curing temperature. In some embodiments, the first material of the solder cap is removed from the sidewall of the via by an etching process and the via is encapsulated in a first encapsulant.

An electrical component including a substrate, a first dielectric layer on the substrate, a redistribution layer pad on the first dielectric layer, and a component interconnection element on the redistribution layer pad so that the component interconnection element fills an opening in the second dielectric layer. The opening includes at least one protrusion between the component interconnection element solder ball metallization and the redistribution layer pad.

A semiconductor package is provided in which a first adhesive film includes a first extension portion extending relative to a side surface of a first semiconductor chip in a second direction, perpendicular to the first direction, the first extension portion has an upper surface including a first recess concave toward a base chip, each of the plurality of second adhesive films includes a second extension portion extending relative to side surfaces of the plurality of second semiconductor chips in the second direction, and the second extension portion has an upper surface including a second recess concave in the first direction and a lower surface including a protrusion in the first recess or the second recess.