H01Q3/38

Antenna device for beam steering and focusing

Provided is an antenna apparatus including: a signal splitter configured to generate a second signal including N equal-phase signals by splitting a first signal received from a signal source; a signal source virtual beam adjustor configured to generate a third signal including N signals by shifting a phase of each signal included in the second signal; a transmission beam adjustor configured to generate a fourth signal including N signals by shifting a phase of each signal included in the third signal by 0 degree or 180 degrees; and a transmitter including N transmission antennas transmitting respectively transmitting the N signals included in the fourth signal.

APPARATUS AND METHODS FOR BEAMFORMING TRACKING

Signals are received from antenna elements in an antenna array, and respective phase shifts are applied to the received signals. The respective phase shifts are relative to a channel phase shift associated with each antenna element, and correspond to side angles from a current antenna beam direction of the antenna array. Control signals based on the phase shifted signals are generated to control the channel phase shifts, to provide beamforming tracking.

APPARATUS AND METHODS FOR BEAMFORMING TRACKING

Signals are received from antenna elements in an antenna array, and respective phase shifts are applied to the received signals. The respective phase shifts are relative to a channel phase shift associated with each antenna element, and correspond to side angles from a current antenna beam direction of the antenna array. Control signals based on the phase shifted signals are generated to control the channel phase shifts, to provide beamforming tracking.

Axially symmetric high-density beamforming topology

Systems, methods, and methods of fabricating can provide an axially symmetric high-density beamforming architecture. The beamforming architecture can include pluralities of symmetric beamforming layers having integrated electronics. The beamforming layers can be incrementally rotated and stacked with respect to each other in three-dimensions (3D) to provide a high-density topology capable of forming thousands of beams in a phased array antenna. The beamforming layers provide signal/beam pathways from a group (or sub-group) of signal interfaces on an input side of the beamforming layer to a corresponding group of signal interfaces on an output side of the beamforming layer. The beamforming architecture can also include a plurality of beam routing layers that mate with the plurality of beamforming layers to route the signals from a plurality of input beamforming layers to a plurality of output beamforming layers.

Axially symmetric high-density beamforming topology

Systems, methods, and methods of fabricating can provide an axially symmetric high-density beamforming architecture. The beamforming architecture can include pluralities of symmetric beamforming layers having integrated electronics. The beamforming layers can be incrementally rotated and stacked with respect to each other in three-dimensions (3D) to provide a high-density topology capable of forming thousands of beams in a phased array antenna. The beamforming layers provide signal/beam pathways from a group (or sub-group) of signal interfaces on an input side of the beamforming layer to a corresponding group of signal interfaces on an output side of the beamforming layer. The beamforming architecture can also include a plurality of beam routing layers that mate with the plurality of beamforming layers to route the signals from a plurality of input beamforming layers to a plurality of output beamforming layers.

BEAMFORMER INTEGRATED CIRCUITS WITH MULTIPLE-STAGE HYBRID SPLITTER/COMBINER CIRCUITS
20230187805 · 2023-06-15 ·

A multiple-stage splitter/combiner circuit includes first and second splitter/combiner circuits coupled together. The first splitter/combiner circuit has first, second, and third input/output (I/O) ports, a first quarter wave line with a first end coupled to the first I/O port and a second end coupled to the second I/O port, a second quarter wave line with a first end coupled to the first I/O port and a second end coupled to the third I/O port, and a first resistor with first and second terminals coupled to the second and third I/O ports, respectively. The second splitter/combiner circuit has fourth, fifth, and sixth I/O ports, and a ring of multiple quarter wave lines, which includes third and fourth quarter wave lines. The third and fourth quarter wave lines each extend from the fourth I/O port in different directions from each other to the fifth and sixth I/O ports, respectively.

BEAMFORMER INTEGRATED CIRCUITS WITH MULTIPLE-STAGE HYBRID SPLITTER/COMBINER CIRCUITS
20230187805 · 2023-06-15 ·

A multiple-stage splitter/combiner circuit includes first and second splitter/combiner circuits coupled together. The first splitter/combiner circuit has first, second, and third input/output (I/O) ports, a first quarter wave line with a first end coupled to the first I/O port and a second end coupled to the second I/O port, a second quarter wave line with a first end coupled to the first I/O port and a second end coupled to the third I/O port, and a first resistor with first and second terminals coupled to the second and third I/O ports, respectively. The second splitter/combiner circuit has fourth, fifth, and sixth I/O ports, and a ring of multiple quarter wave lines, which includes third and fourth quarter wave lines. The third and fourth quarter wave lines each extend from the fourth I/O port in different directions from each other to the fifth and sixth I/O ports, respectively.

FLEXIBLE MULTI-BEAM, MULTI FREQUENCY, WIDEBAND RF AND DIGITAL TRANSCEIVER ARCHITECTURE FOR MODULAR METASURFACE ANTENNA

An antenna transceiver architecture for a modular metasurface antenna and method for using the same are disclosed. In some embodiments, the antenna architecture includes a plurality of metasurface antenna tiles, where each metasurface antenna tile of the plurality of metasurface antenna tiles having one or more feed ports individually fed when in operation to support one or more independent beams, and wherein the plurality of metasurface antenna tiles comprise a plurality of sub-arrays of metasurface antenna tiles. In some embodiments, the antenna architecture also includes a plurality of digital back ends (DBEs) coupled to the plurality of metasurface antenna tiles, where each DBE is operable to: adjust time delays of one or more of received signals arriving from metasurface antenna tiles of the one sub-array of metasurface antenna tiles as part of time delay beamforming and combine the received signals in a digital domain to produce one or more beamformed signals, and delay transmit signals fed to the plurality of tiles in the digital domain by adjusting time delays of one or more of the transmit signals as part of time delay beamforming.

INTEGRATED DIGITAL ACTIVE PHASED ARRAY ANTENNA AND WINGTIP COLLISION AVOIDANCE SYSTEM
20170343667 · 2017-11-30 ·

A radar system to detect and track objects in three dimensions. The radar system including antennae, transmit, receive and processing electronics is all in a small, lightweight, low-cost, highly integrated package. The radar system uses a wide azimuth, narrow elevation radar pattern to detect objects and a Wi-Fi radio to communicate to one or more receiving and display units. One application may include mounting the radar system in an existing radome on an aircraft to detect and avoid objects during ground operations. Objects may include other moving aircraft, ground vehicles, buildings or other structures that may be in the area. The system may transmit information to both pilot and ground crew.

WIRELESS COMMUNICATION APPARATUS, ANTENNA DIRECTIONALITY CONTROL METHOD, AND POWER SUPPLY CIRCUIT

A wireless communication apparatus includes a plurality of phase adjusters configured to adjust the phase of a digital baseband signal d.sup.(k) for k=1, 2, . . . , K (K is a natural number equal to or larger than one) and output a plurality of digital signals d.sub.1.sup.(k), d.sub.2.sup.(k), d.sub.m.sup.(k) (m is a natural number equal to or larger than two) having phases different from each other, an i-th converter configured to convert a signal obtained by synthesizing the digital signals d.sub.i.sup.(1), d.sub.i.sup.(2), . . . , d.sub.i.sup.(K) into an analog signal a.sub.i for i=1, 2, . . . , m, and a power supply circuit including a first stage circuit, a second stage circuit, . . . , an N-th stage circuit (N is a natural number equal to or larger than one).