A pyrolytic graphite (PG) substrate and laser diode package includes a substrate body having a PG crystalline structure with a basal plane oriented at a pre-determined orientation angle as measured from a longitudinal axis of a heat generating material, such as a laser diode, mounted on a surface of the PG substrate, so that a coefficient of thermal expansion (CTE) of the PG substrate is substantially matched with a CTE of the material.

A structure of Vertical Cavity Surface-Emitting Laser (VCSEL) comprises an ion-implanted region with gas-furnace configuration arranged in the second mirror layer around a laser light output window, in order to retain several conductive passages between the inner and outer rims of the ion-implanted region, so as to let the aperture of the inner rim of the metal layer (that is, the aperture of the output window) be expanded without loss of resistance. Not only the shading effect can be removed, the spectrum width suppression function can be preserved, but also various photoelectric characteristics such as transmission eye diagram and photoelectric curve linearity can be improved, in addition, high-speed transmission characteristics can also be optimized.

A Cu—Si—Cu substrate having a silicon substrate, copper plating on opposite sides of the silicon substrate, and copper vias extending thru the silicon substrate to electrically and thermally connect the copper platings together. The thicknesses of the silicon substrate and the copper platings are selected so that a coefficient of thermal expansion (CTE) of the Cu—Si—Cu substrate is substantially the same as a CTE of a material to be mounted on the Cu—Si—Cu substrate.

A single chip including an optoelectronic device on the semiconductor layer in a first region, the optoelectronic device comprises a bottom cladding layer, an active region, and a top cladding layer, wherein the bottom cladding layer is above and in direct contact with the semiconductor layer, the active region is above and in direct contact with the bottom cladding layer, and the top cladding layer is above and in direct contact with the active region, a silicon device on the substrate extension layer in a second region, a device insulator layer substantially covering both the optoelectronic device in the first region and the silicon device in the second region, and a waveguide embedded within the device insulator layer in direct contact with a sidewall of the active region of the optoelectronic device.

In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.

Systems and methods are described herein to grow a layered structure. The layered structure is implemented as a VCSEL and comprises a first germanium substrate layer having a first lattice constant, a second layer that has a second lattice constant and is epitaxially grown over the first germanium substrate layer, wherein the second layer comprises a compound of a first constituent and a second constituent, and a third layer that has a third lattice constant and is epitaxially grown over the second layer, wherein the third layer comprises a compound of a third constituent and a fourth constituent, wherein the first, second, third and fourth constituents are selected such that the layered structure is pseudomorphic and the first lattice constant is between the second lattice constant and the third lattice constant.

The disclosure describes techniques for forming an ohmic contact layer in a wafer containing CMOS devices and attaching a VCSEL die therein. A composite layer that forms the ohmic contact layer is selected based on the epitaxially-grown compound semiconductor material of the VCSEL die. The ohmic contact layer may not comprise gold, as gold introduces contamination in the rest of the CMOS process. The wafer may have an allocated area for accepting the VCSEL die. The allocated area may have a recess to facilitate placement of the VCSEL die.

In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.

A method of manufacturing a light emitting device includes: providing a light source including one or more semiconductor laser elements, an optical member including one or more lens parts, a condensing lens, and a photodetector, one above the other; causing at least one semiconductor laser element to emit light; determining a reference detection position of light; placing a first light-shielding member to shield a portion of the light passed through the lens parts; determining a post-shielding detection position; adjusting a distance between the light source and the optical member based on the reference detection position and the post-shielding detection position; and securing the optical member and the light source to each other.

A CuSiCu substrate having a silicon substrate, copper plating on opposite sides of the silicon substrate, and copper vias extending thru the silicon substrate to electrically and thermally connect the copper platings together. The thicknesses of the silicon substrate and the copper platings are selected so that a coefficient of thermal expansion (CTE) of the CuSiCu substrate is substantially the same as a CTE of a material to be mounted on the CuSiCu substrate.