Current leakage interrupter, having a shell consisting of an upper shell and a lower shell, a PCB inside the shell, a detection device and a trip device mounted to the PCB, power lines electrically connected to the trip device through the detection device, and pins electrically connected to the trip device. The lower shell has pin holes; front ends of the pins extend out of the pin holes. A reverse hook is provided at an inner side of the lower shell at an edge of each pin hole to fix onto a first side of a rear end of a corresponding pin; a second side of the rear end of each pin is extended and bended into a bended portion; a supporting seat is also provided at the inner side of the lower shell at the edge of each pin hole to support the bended portion of the corresponding pin.

A multiphase ground fault circuit interrupter includes a first phase power line input, a second phase power line input, a third phase power line input, a neutral line input, a controller circuit having a relay control output, a first phase latching relay having a first phase switch input coupled to the first phase power line input and a first phase relay control input coupled to the relay control output of the controller circuit, a sensor having a core and a sensor pickup coupled to the controller circuit, and a first phase load wire coupled to a first phase switch output of the first phase latching relay and passed through the core.

Passive monitoring the integrity of current sensing devices and associated circuitry in GFCI and AFCI protective devices is provided. A protection circuit interrupter employs a capacitively coupled noise signal obtained by an arrangement of one or both of line side arms relative to a Rogowski coil. The noise signal is monitored while the line and load sides of a protective circuit interrupter are disconnected, and the connection of the line and load sides disabled if the noise signal fails to correlate sufficiently to a reference noise cycle. When the line and load sides are connected, the RMS value of the observed current signal is monitored such that the line and load sides are disconnected if the observed current signal fails to meet an RMS threshold. The observed current signal is compensated by subtracting the reference noise cycle prior to monitoring for the fault condition applicable to the protective device.

A fault detector detects grounded-neutral faults. The fault detector is configured to: receive a first signal from a first induction circuit, the first induction circuit configured to detect a current imbalance between a line conductor and a neutral conductor; determine a first frequency and a first phase of a noise signal component of the first signal; output a noise cancellation signal to a primary side of the first induction circuit, the noise cancellation signal having the first frequency of the noise signal component and an opposite phase than the first phase of the noise signal component; and generate a trip signal based on determining that an impedance of the neutral conductor to ground is at or below a threshold level based upon the first signal received during the injection of the noise cancelation signal.

A ground fault circuit interrupter (GFCI) including separable contacts, a ground fault detection circuit structured to detect a ground fault based and to output a trip signal in response to detecting the ground fault, a trip circuit structured to trip open the separable contacts in response to the trip signal, a test button structured to be actuated by a user, a test unit structured to sequentially perform a GFCI self-test sequence and a ground fault test sequence in response to actuation of the test button, wherein the test unit is structured to determine whether the GFCI passed the GFCI self-test sequence and to output in an alarm signal in response to determining that the GFCI failed the GFCI self-test sequence, and an indicator structured to receive the alarm signal and to provide a visual or audible indication in response to receiving the alarm signal.

The invention discloses a circuit protection device with self fault detection function. The ground fault protection unit comprises a ground fault detection circuit, an AC power supply path and an electromagnetic drive circuit. The self fault detection unit comprises an automatic detection circuit and a control circuit. The control circuit starts periodically a self fault detection process, controls the automatic detection circuit to generate a ground fault current GFC to the ground fault protection unit, and detects the fault status signal from the electromagnetic drive circuit. Based on the fault status signal, operation situations of the ground fault protection unit can be determined. If a fault occurs, an emergency interruption signal is generated, and that activates the electromagnetic drive circuit to make the ground fault protection unit trip in emergency, and cut off the AC power supply on load and socket terminals, and thus the emergency protection function is achieved. The ground fault protection unit utilizes an electromagnetic drive circuit which comprises two silicon controlled rectifiers, so that the reliability of the circuit protection device can be improved.

Passive monitoring the integrity of current sensing devices and associated circuitry in GFCI and AFCI protective devices is provided. A protection circuit interrupter employs a capacitively coupled noise signal obtained by an arrangement of one or both of line side arms relative to a Rogowski coil. The noise signal is monitored while the line and load sides of a protective circuit interrupter are disconnected, and the connection of the line and load sides disabled if the noise signal fails to correlate sufficiently to a reference noise cycle. When the line and load sides are connected, the RMS value of the observed current signal is monitored such that the line and load sides are disconnected if the observed current signal fails to meet an RMS threshold. The observed current signal is compensated by subtracting the reference noise cycle prior to monitoring for the fault condition applicable to the protective device.

A circuit for a circuit interrupter is provided. The circuit may in include a first SCR configured to receive a first trigger signal at a gate of the first SCR, a second SCR configured to receive a second trigger signal at a gate of the second SCR, and a third SCR configured to receive a third trigger signal at a gate of the third SCR. A cathode of the first SCR may be connected to an anode of the third SCR. A cathode of the second SCR and a cathode of the third SCR may be connected to a ground. Methods of operating a circuit interrupter and a circuit are also provided.

A circuit interrupting device that includes a line conductor, a load conductor, an interrupting device, a delay circuit, and a fault detection circuit. The interrupting device disconnects the line conductor from the load conductor when the circuit interrupting device is in a tripped condition. The delay circuit includes a first switch, a second switch, and a third switch, and delays the disconnecting of the line conductor from the load conductor. The fault detection circuit detects a fault condition and generates a fault detection signal when the fault condition is detected. The fault detection circuit provides the fault detection signal to the first switch to trigger the first switch, and the delay circuit delays the triggering of the second switch and the third switch. After an amount of time has elapsed, the second switch and the third switch are triggered to place the circuit interrupting device in the tripped condition.

Implementations of ground fault circuit interrupter (GFCI) self-test circuits may include: a current transformer coupled to a controller, a silicon controlled rectifier (SCR) test loop coupled to the controller, a ground fault test loop coupled to the controller, and a solenoid coupled to the controller. The SCR test loop may be configured to conduct an SCR self-test during a first half wave portion of a phase and the ground fault test loop may be configured to conduct a ground fault self-test during a second half wave portion of a phase. An SCR may be configured to activate the solenoid to deny power to a load upon one of the SCR self-test or the ground fault self-test being identified as failing.