A switching power conversion circuit includes a conversion capacitor, a capacitive power conversion circuit, an inductor, an inductive power conversion circuit and a switching control circuit. The capacitive power conversion circuit switches the conversion capacitor periodically according to a switching control signal generated by the switching control circuit, to generate a first intermediate voltage and a first proportional voltage in a promptly rising mode and to generate a second intermediate voltage and a second proportional voltage in a promptly falling mode. In the promptly rising mode, a rising slope of an inductor current is determined by a difference between a high level of the first proportional voltage and an output voltage. In the promptly falling mode, a falling slope of the inductor current is determined by a difference between a low level of the second proportional voltage and the output voltage.

A charge pump circuit includes a boost capacitor driven by a first clock signal and a bootstrap capacitor driven by a second clock signal. The first and second clock signals have different duty cycles, with the duty cycle of the second clock signal being smaller than the duty cycle of the first clock signal. An input transistor is coupled between an input node and a boost node coupled to the boost capacitor. The control terminal of the input transistor is coupled to the bootstrap capacitor. A bootstrap transistor coupled between the boost node and the control terminal of the input transistor is driven by a logical inverse of the first clock signal.

A bipolar output charge pump circuit having a network of switching paths for selectively connecting an input node and a reference node for connection to an input voltage, a first pair of output nodes, two pairs of flying capacitor nodes, and a controller for controlling the switching of the network of switching paths. The controller is operable to control the network of switching paths when in use with two flying capacitors connected to the two pairs of flying capacitor nodes, to provide a first mode and a second mode when in use with two flying capacitors connected to the flying capacitor nodes, wherein at least the first mode corresponds to a bipolar output voltage of +/−3 VV, +/−VV/5 or +/−VV/6.

A DC to DC converter includes an input configured to receive a DC input voltage, an output and two serially connected capacitors connected across the output. The two serially connected capacitors include a first capacitor and a second capacitor connected together at a connection node. The converter also includes a first parallel converter connected between the input and the connection node, a second parallel converter connected between the input and the connection and in parallel with the fist parallel converter, and a controller that selectively connects the first and second parallel converters to the input based on a desired magnitude and polarity of a voltage at the output.

A switch activation system including a charge pump, a load monitor, and a switch driver. The charge pump drives a negative voltage node to a predetermined negative voltage level. The load monitor monitors the charge pump and to assert a break done signal after the charge pump begins driving the negative voltage back to the predetermined negative voltage level after being increased. The switch driver turns on a first electronic switch in response to assertion of a corresponding activation signal and assertion of the break done signal. The break done signal is asserted only after electronic switches being turned off are fully turned off to avoid conflict. The charge pump operates at a frequency based on a difference between a voltage level of the negative voltage node and the predetermined negative voltage level to drive the negative voltage node back to its predetermined level within a predetermined period of time.

Disclosed in the present invention are a charge pump circuit, a chip, and a communication terminal. The charge pump circuit comprises a phase clock generation module, an acceleration response control module, and a plurality of sub charge pump modules. By generating a plurality of clock signals with a fixed phase difference by means of the phase clock generation module, correspondingly controlling the plurality of sub charge pump modules to generate output voltages, and by means of the acceleration response control module, measuring the output voltage of each sub charge pump module, and separately outputting a logic signal to the phase clock generation module and each sub charge pump module, the frequency of the clock signals outputted by the phase clock generation module is changed, and the charge and discharge time of a capacitor in each sub charge pump module is reduced.

A positive-and-negative-voltage charge pump circuit, comprising a clock generation module, a positive-voltage charge pump module, a transient enhancement module, and a negative-voltage charge pump module. The positive-voltage charge pump module generates a positive voltage according to a clock signal output by the clock generation module, and the transient enhancement module is used to sample the positive voltage and a power supply voltage, and convert same into currents for comparison, such that the negative-voltage charge pump module provides a switchable input voltage according to a comparison result. The negative-voltage charge pump module can quickly and reliably establish a negative voltage according to a clock signal output by the clock generation module, thereby improving the speed and efficiency of the negative-voltage charge pump module generating the negative voltage. Further disclosed are an integrated circuit chip, which comprises the positive-and-negative-voltage charge pump circuit, and a communication terminal.

Low noise charge pumps are disclosed. In certain embodiments, a charge pump includes a charge pump output terminal configured to provide a charge pump voltage, a switched capacitor, an inverter having an output electrically connected to a first end of the switched capacitor, a pair of charging switches connected between a second end of the switched capacitor and a reference voltage, and a pair of discharging switches connected between the second end of the switched capacitor and the charge pump output terminal. The pair of charging switches is closed during a charging operation and open during a discharging operation, while the pair of discharging switches closed during the discharging operation and open during the charging operation.

The present technology is generally directed to implantable medical device systems configured to provide cardiac resynchronization therapy. In some embodiments, the implantable medical device system comprises a housing, electrodes carried by the housing, a transducer configured to produce input voltage signals in response to ultrasound energy, and a circuit configured to provide, via an electrical pathway, output voltage signals based on the input voltage signals. The circuit comprises a movable switch, and a slew rate detector configured to detect whether a voltage rate of an individual pulse of the input voltage signals exceeds a predetermined threshold voltage rate. The circuit is configured to move the switch to an open position in response to the detected voltage rate exceeding the predetermined threshold voltage rate.

Low noise charge pumps are disclosed. In certain embodiments, a charge pump includes a charge pump output terminal configured to provide a charge pump voltage, a switched capacitor, an inverter having an output electrically connected to a first end of the switched capacitor, a pair of charging switches connected between a second end of the switched capacitor and a reference voltage, and a pair of discharging switches connected between the second end of the switched capacitor and the charge pump output terminal. The pair of charging switches is closed during a charging operation and open during a discharging operation, while the pair of discharging switches closed during the discharging operation and open during the charging operation.