The disclosure relates to a transducer assembly like a microphone including a bias circuit having a charge pump and a filter circuit coupled to a transducer. The filter circuit includes a voltage-controlled resistor located between an output of the charge pump and the transducer, and a capacitor coupled to the voltage-controlled resistor opposite the charge pump, wherein the bias circuit is configured with a larger bandwidth for faster settling during transient operation than during steady-state operation.

Circuits/methods for controlling the startup of multiple parallel power converters that avoid inrush current or switch overstress in an added power converter or a power converter having fault conditions. Embodiments include node status detectors coupled to nodes within parallel-connected power converters to monitor voltage/current and configured in some embodiments to work in parallel with an output status detector measuring the startup output voltage of a power converter. With charge pump-based power converters, the node status detectors ensure that the power converter pump capacitors are charged while the output capacitor is charged as well. For such embodiments, a softstart period of startup may be considered finished if both the shared output capacitors and the power converter pump capacitors are charged to target values. Embodiments may also be used for fault detection during steady-state operation.

In a power converter, a switching network having switches that operate at a common frequency and duty cycle interconnects circuit elements. These circuit elements include capacitors that are in a capacitor network and a magnetic filter. When connected to the capacitors by a switch from the switching network, the magnetic filter imposes a constraint upon inter-capacitor charge transfer between the capacitors to maintain the filter's second terminal at a voltage. The switching network transitions between states. These states include a first state, a second state, and a third state. In both the first state and the third state, the first magnetic-filter terminal couples to the capacitor network. In the second state, which occurs between the first and third state, the switches ground the first magnetic-filter terminal.

Charge pump stages are coupled between flying capacitor pairs and arranged in a cascaded between a bottom voltage line and an output voltage line. Gain stages apply pump phase signals having a certain amplitude to the charge pump stages via the flying capacitors. A feedback signal path from the output voltage line to the bottom voltage line applies a feedback control signal to the bottom voltage line. Power supply for the gain stages is provided by a voltage of the feedback control signal in order to control the amplitude of the pump phase signals. An asynchronous logic circuit generates the switching drive signals for the gain stages with a certain switching frequency which is a function of a logic supply voltage derived from the voltage of the feedback control signal.

A charge pump circuit is provided. The charge pump circuit includes a dual-phase charge pump, a first load switch, a second load switch, and a control circuit. The dual-phase charge pump performs a voltage pumping operation on a power source in response to a first clock and a second clock to generate a first pumping voltage at a first node and a second pumping voltage at a second node. The control circuit controls the first load switch in response to a third clock and controls the second load switch in response to a fourth clock. In a period during which the first load switch is turned off, the second load switch transfers the first pumping voltage to an output terminal of the charge pump circuit. In a period during which the second load switch is turned off, the first load switch transfers the second pumping voltage to the output terminal.

A demultiplexer includes: a first transistor connected between a data input terminal and a first output terminal; a second transistor connected between the data input terminal and a second output terminal; and a first pre-charge circuit connected to a gate electrode of the first transistor, the first pre-charge circuit including: a third transistor and a first diode connected between a first clock input terminal and the gate electrode of the first transistor in parallel; and a first capacitor connected between a second clock input terminal and the gate electrode of the first transistor.

Disclosed herein are non-limiting examples of voltage generators that use multiple charge pumps coupled in series to generate a targeted voltage. The charge pumps implement multiple charge pump units that reduce the introduction of noise into a circuit in which they are implemented. The charge pumps units work in parallel on different clock phases to reduce spurious noise. This is in contrast to using a single charge pump with a relatively large flying capacitor or a plurality of charge pumps in series. This can, for example, reduce spurious signals or spurs that arise due at least in part to the characteristics of the clock signal. The disclosed technologies may be particularly advantageous for SOI-based components and circuits.

A charge pump circuit includes a power switch, a first pull-low circuit, an output pull-low circuit, a first charge pump stage and an output charge pump stage. The power switch receives an enabling signal. The first pull-low circuit and the output pull-low circuit receive a pull-low signal. The first charge pump stage includes a first boost capacitor used to receive a first phase signal, a first transfer transistor, a first gate-control transistor and a first storage capacitor used to receive a second phase signal. The output charge pump stage includes an output boost capacitor used to receive a third phase signal, an output transfer transistor and an output gate-control transistor. The charge pump circuit generates voltages in an erasing operation, a program operation and a read operation according to the enabling signal, the pull-low signal, the first phase signal, the second phase signal and the third phase signal.

Transient or fault conditions for a switched capacitor power converter are detected by measuring one or more of internal voltages and/or currents associated with switching elements (e.g., transistors) or phase nodes, or voltages or currents at terminals of the converter, and based on these measurements detect that a condition has occurred when the measurements deviate from a predetermined range. Upon detection of the condition fault control circuitry alters operation of the converter, for example, by using a high voltage switch to electrically disconnect at least some of the switching elements from one or more terminals of the converter, or by altering timing characteristics of the phase signals.

A hybrid power converter circuit includes a switched-capacitor power converter stage and a pulse-width modulation (PWM) or resonant output circuit coupled to a switching node of the switched-capacitor power converter stage. In particular, the PWM or resonant output circuit can include a transformer having a primary winding and a secondary winding magnetically coupled to each other, and the secondary winding is coupled to the output node of the power converter. The switched-capacitor power converter stage is coupled between the input node of the power converter and the primary winding of the transformer, and includes capacitors and switches configured to connect the capacitors to the input node during a first phase of operation and connect the capacitors to the primary winding of the transformer of the PWM or resonant output circuit during a second phase of operation.