Patent classifications
H02M3/073
DC-DC TRANSFORMER WITH INDUCTOR FOR THE FACILITATION OF ADIABATIC INTER-CAPACITOR CHARGE TRANSPORT
In a power converter, a switching network having switches that operate at a common frequency and duty cycle interconnects circuit elements. These circuit elements include capacitors that are in a capacitor network and a magnetic filter. When connected to the capacitors by a switch from the switching network, the magnetic filter imposes a constraint upon inter-capacitor charge transfer between the capacitors to maintain the filter's second terminal at a voltage. The switching network transitions between states. These states include a first state, a second state, and a third state. In both the first state and the third state, the first magnetic-filter terminal couples to the capacitor network. In the second state, which occurs between the first and third state, the switches ground the first magnetic-filter terminal.
Charge pump and switch control circuit
A charge pump includes: a first diode that is connected to a first node; a second diode that is connected to a second node; a pump capacitor that is connected to a third node to which the first diode and the second diode are connected; a power supply capacitor that is connected to the pump capacitor; a third diode that is connected between the pump capacitor and the power supply capacitor; and a zener diode that is connected in parallel to the third diode and the power supply capacitor. A power supply device decreases a ripple of an output current using a ripple reduction signal.
Charge pump circuit and semiconductor device including the same
Efficiency of a charge pump circuit is increased. The charge pump circuit includes serially connected fundamental circuits each including a diode-connected transistor and a capacitor. At least one transistor is provided with a back gate, and the back gate is connected to any node in the charge pump circuit. For example, the charge pump circuit is of a step-up type; in which case, if the transistor is an n-channel transistor, a back gate of the transistor in the last stage is connected to an output node of the charge pump circuit. Back gates of the transistors in the other stages are connected to an input node of the charge pump circuit. In this way, the voltage holding capability of the fundamental circuit in the last stage is increased, and the conversion efficiency can be increased because an increase in the threshold of the transistors in the other stages is prevented.
CHARGE PUMP CIRCUIT OUTPUTTING HIGH VOLTAGE WITHOUT HIGH VOLTAGE-ENDURANCE ELECTRIC DEVICES
The charge pump circuit includes multiple boosting stages, and each stage includes following units. A first switch circuit is controlled by a first clock signal to couple a second terminal of a first capacitor to a first input terminal or a second input terminal. A third switch circuit is controlled by a second clock signal to couple a second terminal of a second capacitor to the first input terminal or the second input terminal. A second switch circuit is controlled by electric potentials on the second capacitor to couple a first terminal of the first capacitor to the first input terminal or an output terminal. The fourth switch circuit is controlled by electric potentials on the first capacitor to couple a first terminal of the second capacitor to the first input terminal or the output terminal.
Power supply for gate driver in switched-capacitor circuit
An apparatus includes first and second pluralities of switches, a controller for controlling these switches, gate-drivers for driving switches from the first plurality of switches, and first and second terminals configured for coupling to corresponding first and second external circuits at corresponding first and second voltages. During operation, the controller causes the first plurality of switches to transition between states. These transitions result in the second voltage being maintained at a value that is a multiple of the first voltage. The controller also causes the second plurality of switches to transition between states. These transitions resulting in capacitors being coupled or decoupled from the second voltage. The gate drivers derive, from the capacitors, charge for causing a voltage that enables switches from the first plurality of switches to be driven.
Memory device capable of improving erase and program efficiency
A memory device includes a first well, a second well, a first active area, a second active area, a third active area, a first poly layer and a second poly layer. The first well is of a first conductivity type. The second well is of a second conductivity type different from the first conductivity type. The first active area is of the second conductivity type and is formed on the first well. The second active area is of the first conductivity type and is formed on the first well and between the first active area and the second well. The third active area is of the first conductivity type and is formed on the second well. The first poly layer is formed above the first well and the second well. The second poly layer is formed above the first well.
Electroactive polymer actuator device and driving method
An actuator device comprises an electroactive polymer actuator (116) and a control circuit for driving the electroactive polymer actuator. The control circuit comprises a voltage boosting circuit including at least a capacitor (114; C11, C12, C13). An electroactive polymer layer (110) forms the electroactive polymer actuator in an active region (112) as well as a dielectric layer of the capacitor in a passive region (111). This provides integration of components to enable cost reductions and miniaturization.
INTELLIGENT CHARGE PUMP ARCHITECTURE FOR FLASH ARRAY
The present disclosure relates to a non-volatile memory device and to a method for generating overvoltage values in such a memory device structured in a plurality of sub-arrays and including at least a decoding and sensing circuitry associated with each sub-array, a charge pump architecture for each sub-array including pump stages for increasing the value of an input voltage and obtaining an overvoltage output value, a control and JTAG interface in the memory device, and at least a registers block coupled to the charge pump architecture and driven by a logic circuit portion for receiving at least an activation signal selecting a specific charge pump architecture associated with a memory sub-array of the plurality of sub-arrays.
Charge pump stability control
An apparatus for power conversion includes a switching network that controls interconnections between pump capacitors in a capacitor network that has a terminal coupled to a current source, and a charge-management subsystem. In operation, the switching network causes the capacitor network to execute charge-pump operating cycles during each of which the capacitor network adopts different configurations in response to different configurations of the switching network. At the start of a first charge-pump operating cycle, each pump capacitor assumes a corresponding initial state. The charge-management subsystem restores each pump capacitor to the initial state by the start of a second charge-pump operating cycle that follows the first charge-pump operating cycle.
VOLTAGE DOUBLING CIRCUIT FOR LAUNDRY TREATING APPLIANCE WITH HIGH POWER VARIABLE FREQUENCY DRIVE
A circuit that increases input voltage to higher output voltage connected to a variable frequency drive in an appliance. Several switching arrangements, timing, and safety mechanisms are in place to assist. When the circuit experiences high draw, high voltage output values of circuit decrease over time, but different aspects of the circuit can be constructed so that the amount of time required at a higher voltage does not exceed the amount of time in which the high voltage output is provided.