A switched-mode power regulator circuit has four solid-state switches connected in series and a capacitor and an inductor that regulate power delivered to a load. The solid-state switches are operated such that a voltage at the load is regulated by repetitively (1) charging the capacitor causing a current to flow in the inductor and (2) discharging the capacitor causing current to flow in the inductor. The power regulator circuit may be configured to operate with zero current switching at frequencies in the range of 100 MHz, enabling it to be fabricated on a unitary silicon die along with the load that it powers.

A DC/DC converter includes: duty command calculation units for calculating duty command values for first, second, third, and fourth switching elements on the basis of difference voltage between a high-voltage-side voltage command value and a high-voltage-side voltage detection value; and a phase shift duty command calculation unit for calculating a phase shift duty command value corresponding to a phase difference between gate signals for the first and fourth switching elements and gate signals for the second and third switching elements, on the basis of difference voltage between a voltage target value and a charge voltage detection value of a charge/discharge capacitor, wherein gate signals for driving the first, second, third, fourth switching elements are generated on the basis of the duty command values and the phase shift duty command value.

Described examples include DC to DC converters and systems with switching circuitry formed by four series-connected switches, inductors connected between the ends of the switching circuitry and corresponding output nodes, and with a flying capacitor coupled across interior switches of the switching circuitry and a second capacitor coupled across the ends of the switching circuitry. A control circuit operates the switching circuit to control a voltage signal across the output nodes using a first clock signal and a phase shifted second clock signal to reduce output ripple current and enhance converter efficiency using valley current control. The output inductors are wound on a common core in certain examples.

A multilevel converter system is provided. The system includes a converter and a converter controller interfaced with the converter. The converter controller includes a voltage loop, a current loop, and a voltage compensation loop. The voltage loop is configured to receive first and second voltages from the first and second segments of the converter and a reference voltage. The current loop is configured to receive a current output of the converter, a reference current, and a balancing reference current. The voltage compensation loop is configured to receive the first and second voltages and a sign signal. The converter controller is configured to generate first and second pulse-width modulation (PWM) signals using output signals from the current loop and the output compensation signals from the voltage compensation loop. The PWM signals are configured to control the switches of the converter and to balance the first voltage with the second voltage.

The present application relates to switching power supplies and in particular to AC to DC switch mode power supplies, to methods of power factor correction for same and to devices and circuits that may be used generally in same. The application describes a number of multi-level approaches and circuits.

A multi-level power converter comprising: n input stages (Ein_n), n being at least equal to 1, each input stage comprising n+1 identical input converters (CONVx_En) connected together, the input converters (CONVx_En) exhibiting an identical topology, chosen from among the architectures of the NPC (Neutral Point Clamped), ANPC (Active Neutral Point Clamped), NPP (Neutral Point Piloted) and SMC (Stacked Multicell Converter); an output stage (Eout) connected to the input stage of rank 1 and comprising an output converter (CONVs) supplied with a differential voltage (Vfloat) resulting from a first electrical potential applied to the output of a first input converter of the input stage of rank 1 and from a second electrical potential applied to the output of a second input converter of the input stage of rank 1, the output converter (CONVs) exhibiting a topology chosen from among an architecture with floating capacitor (FC), SMC (Stacked Multicell Converter), NPC (Neutral Point Clamped), NPP (Neutral Point Piloted) and ANPC (Active Neutral Point Clamped).

Techniques and apparatus for current-based transitioning between a buck converter mode and a charge pump mode in an adaptive combination power supply circuit. One example power supply circuit generally includes a switching regulator and control logic coupled to the switching regulator. The control logic is generally configured to compare an indication of a current associated with the switching regulator to a threshold and to control a transition of the switching regulator between a buck converter mode and a charge pump mode based on the comparison.

A power converter with an automatic balance mechanism of a flying capacitor is provided. The flying capacitor and a first terminal of an output inductor are connected to a switch circuit. Two terminals of an output capacitor are respectively connected to a second terminal of the output inductor and grounded. Two input terminals of an error amplifier are respectively connected to a node between the output capacitor and the output inductor, and coupled to a reference voltage. The error amplifier outputs an error amplified signal according to a voltage of the node and the reference voltage. A comparator circuit receives a ramp signal. A slope of the ramp signal is proportional to a voltage of the flying capacitor. The comparator circuit compares the ramp signal with the error amplified signal to output a comparison signal. The driving circuit drives the switch circuit according to the comparison signal.

Generalized circuit topology of voltage level multiplier modules (VLMMs) for use with multilevel inverters (MLIs) and power converter circuits comprising at least one VLMM and a MLI are described herein. The VLMM is configured to receive a first output voltage from the MLI having a first number of voltage levels and to generate a second output voltage having a second number of voltage levels. If the first number of voltage levels is M, and the VLMM is N-fold voltage level multiplier, then second number of voltage levels is M×N+1. Switching pattern generators for use with the VLMM and modulation methods for controlling switching elements of the VLMM are also described herein.

In a multilevel power conversion circuit, output harmonic waves and electromagnetic noise can be reduced as the number of output levels is increased. This, however, increases the number of elements constituting the circuit, causing the degree of difficulty in mounting to increase, cost to increase, and reliability to decrease. It is necessary to provide a circuit configuration, a design method, and a mounting method for obtaining, at low cost, a multilevel power conversion circuit using a large number of elements. A power conversion circuit is used as a unit module and is equipped with input and output terminals each mounted on the main circuit in an open state, wherein the input and output terminals have a mechanism by which the input and output terminals can be flexibly interconnected with the input and output terminals of another same module. A plurality of the highly expandable power conversion circuit modules are used and combined using various connection methods to obtain multilevel power conversion circuits having various configurations. This makes it possible to change power conversion circuit performances and characteristics, such as the number of levels, voltage, current, power, the number of phases, etc., only by reconfiguring the modules and to provide a multilevel power conversion circuit most suitable for various applications at low cost.