Patent classifications
H02M7/487
AC/DC CONVERTER STAGE FOR CONVERTER SYSTEM WITH INPUT SERIES STRUCTURE WITH IMPROVED COMMON MODE PERFORMANCE
An AC/DC converter stage for a converter system with an input series structure. The AC/DC converter stage includes two input terminals for inputting an AC input voltage and at least a first circuit branch with at least two switches that are electrically connected in series at a first connection point, where a first input terminal of the two input terminals is electrically connected to the first connection point of the first circuit branch. At least one first electrical storage provides a DC output voltage and is electrically connected in parallel to the first circuit branch. At least one controllable bidirectional switch is electrically connected between the two input terminals.
Method of control of a system comprising a single-phase three-level T type quasi-Z source inverter connected to an LC filter which is in turn connected to a load
A method relating to control of a system including a single-phase three-level quasi-Z type source inverter connected to an LC filter which is in turn connected to a load, the inverter including first and second bridge arms, each including a plurality of switches, the method including the steps of (a) for each of a plurality of consecutive sampling periods (i) determining the duration of a shoot-through period for the next sampling period during which the inverter is in shoot-through mode; (ii) choosing a configuration of the switches for the next sampling period (iii) at the end of the sampling period setting the switches in the chosen configuration for the next sampling period; and (b) at a time during the next sampling period and for the duration of the shoot-through period setting the switches such that the inverter is in shoot-through mode.
Method of control of a system comprising a single-phase three-level T type quasi-Z source inverter connected to an LC filter which is in turn connected to a load
A method relating to control of a system including a single-phase three-level quasi-Z type source inverter connected to an LC filter which is in turn connected to a load, the inverter including first and second bridge arms, each including a plurality of switches, the method including the steps of (a) for each of a plurality of consecutive sampling periods (i) determining the duration of a shoot-through period for the next sampling period during which the inverter is in shoot-through mode; (ii) choosing a configuration of the switches for the next sampling period (iii) at the end of the sampling period setting the switches in the chosen configuration for the next sampling period; and (b) at a time during the next sampling period and for the duration of the shoot-through period setting the switches such that the inverter is in shoot-through mode.
System and method for operating multi-level power converter using a multi-state deadtime
A method for operating a multi-level bridge power converter of an electrical power system connected to a power grid includes providing a plurality of switching devices of the power converter in one of a neutral point clamped topology or an active neutral point clamped topology, the plurality of switching devices including a first group and a second group of switching devices. The method also includes providing a multi-state deadtime for the first and second groups of switching devices that changes based on different state transitions of the power converter. Further, the method includes operating the first and second groups of switching devices according to the multi-state deadtime to allow the first group to switch differently than the second group during the different state transitions, thereby decreasing voltage overshoots on the first group during one or more of the different state transitions and providing safe transition between commutation states of the power converter.
System and method for operating multi-level power converter using a multi-state deadtime
A method for operating a multi-level bridge power converter of an electrical power system connected to a power grid includes providing a plurality of switching devices of the power converter in one of a neutral point clamped topology or an active neutral point clamped topology, the plurality of switching devices including a first group and a second group of switching devices. The method also includes providing a multi-state deadtime for the first and second groups of switching devices that changes based on different state transitions of the power converter. Further, the method includes operating the first and second groups of switching devices according to the multi-state deadtime to allow the first group to switch differently than the second group during the different state transitions, thereby decreasing voltage overshoots on the first group during one or more of the different state transitions and providing safe transition between commutation states of the power converter.
Power Conversion Device and Metal Processing Device
A power conversion device capable of shortening the time required for acceleration of a motor and a metal processing device including the power conversion device are provided. Then, a power conversion device 10 includes a converter 100 configured to convert an AC voltage from outside to a DC voltage Vo and a converter controller 107 configured to control the converter 100. The converter 100 includes a voltage doubler circuit 104 configured to boost the DC voltage Vo when activated, and outputs the DC voltage Vo having a voltage value different in accordance with the activation and stop of the voltage doubler circuit 104. The converter controller 107 activates the voltage doubler circuit 104 at a first time that is earlier by a predetermined period than a second time at which a speed command value ω* of the motor 130 rises from a predetermined value.
THREE-LEVEL INVERTER, CONTROL METHOD, AND SYSTEM
Example three-level inverters, control methods, and systems are provided. One example three-level inverter includes a first bus capacitor, a second bus capacitor, a power conversion circuit, and a controller. The first bus capacitor is connected in the middle of the current bus and the power conversion circuit. The power conversion circuit is configured to convert a direct current into a three-phase alternating current for output. The controller is configured to determine a balance reference by using a difference between absolute values of voltages of the positive and negative direct current buses and an even harmonic current in a grid-connected current, where the balance reference is used to enable the three-level inverter to generate a current signal for balancing the voltages of the positive and negative direct current buses.
THREE-LEVEL INVERTER, CONTROL METHOD, AND SYSTEM
Example three-level inverters, control methods, and systems are provided. One example three-level inverter includes a first bus capacitor, a second bus capacitor, a power conversion circuit, and a controller. The first bus capacitor is connected in the middle of the current bus and the power conversion circuit. The power conversion circuit is configured to convert a direct current into a three-phase alternating current for output. The controller is configured to determine a balance reference by using a difference between absolute values of voltages of the positive and negative direct current buses and an even harmonic current in a grid-connected current, where the balance reference is used to enable the three-level inverter to generate a current signal for balancing the voltages of the positive and negative direct current buses.
Circuit assembly for neutral point clamped inverters that are protected from incorrect commutations
A neutral point clamped inverter with an upper half-bridge and a lower half-bridge, wherein each half-bridge has an inner transistor and an outer transistor, where the inner transistor of the upper half-bridge is configured to interact with the outer transistor of the upper half-bridge such that a signal that reproduces the switch state of the inner transistor is coupled into an actuation circuit for switching the outer transistor and influences the switch state of the outer transistor.
Circuit assembly for neutral point clamped inverters that are protected from incorrect commutations
A neutral point clamped inverter with an upper half-bridge and a lower half-bridge, wherein each half-bridge has an inner transistor and an outer transistor, where the inner transistor of the upper half-bridge is configured to interact with the outer transistor of the upper half-bridge such that a signal that reproduces the switch state of the inner transistor is coupled into an actuation circuit for switching the outer transistor and influences the switch state of the outer transistor.