A microcontroller unit for controlling a three-level inverter including delayed fault protection is provided. The microcontroller unit includes an input port configured to receive a trip signal from a fault detection module, and a plurality of EPWM modules, each configured to control a power switch within the three-level inverter. The microcontroller unit includes an auxiliary EPWM module configured to receive the trip signal and produce a delayed trip signal, and processing circuitry coupled with the input port, the plurality of EPWM modules, and the auxiliary EPWM module. The processing circuitry is configured to, in response to activation of the trip signal, direct one of the plurality of EPWM modules to shut off its corresponding power switch upon activation of the trip signal, and to direct a different one of the plurality of EPWM modules to shut off its corresponding power switch upon activation of the delayed trip signal.

A microcontroller unit for controlling a three-level inverter including delayed fault protection is provided. The microcontroller unit includes an input port configured to receive a trip signal from a fault detection module, and a plurality of EPWM modules, each configured to control a power switch within the three-level inverter. The microcontroller unit includes an auxiliary EPWM module configured to receive the trip signal and produce a delayed trip signal, and processing circuitry coupled with the input port, the plurality of EPWM modules, and the auxiliary EPWM module. The processing circuitry is configured to, in response to activation of the trip signal, direct one of the plurality of EPWM modules to shut off its corresponding power switch upon activation of the trip signal, and to direct a different one of the plurality of EPWM modules to shut off its corresponding power switch upon activation of the delayed trip signal.

Embodiments of the present application disclose a multi-level inverter clamping modulation method and apparatus, and an inverter. Switching elements of an inverter are controlled when an output voltage of the inverter crosses zero, and switching elements in each inverter bridge arm of an active clamp multi-level inverter include an internal tube, an external tube, and a clamping tube. The internal tube and the external tube are connected in series between a positive bus and a negative bus, the clamping tube is connected between a common terminal of the internal tube and the external tube and a bus, the internal tube is a low-frequency switching element, and the external tube and the clamping tube are high-frequency switching elements.

Embodiments of the present application disclose a multi-level inverter clamping modulation method and apparatus, and an inverter. Switching elements of an inverter are controlled when an output voltage of the inverter crosses zero, and switching elements in each inverter bridge arm of an active clamp multi-level inverter include an internal tube, an external tube, and a clamping tube. The internal tube and the external tube are connected in series between a positive bus and a negative bus, the clamping tube is connected between a common terminal of the internal tube and the external tube and a bus, the internal tube is a low-frequency switching element, and the external tube and the clamping tube are high-frequency switching elements.

A dual multi-level inverter topology with reduced switch count and small DC-link capacitor is provided. The inverter topology provides multi-level inverter operation without requiring a neutral point connection that is commonly present in a stacked capacitor topology (for example, a topology including two capacitors).

A dual multi-level inverter topology with reduced switch count and small DC-link capacitor is provided. The inverter topology provides multi-level inverter operation without requiring a neutral point connection that is commonly present in a stacked capacitor topology (for example, a topology including two capacitors).

A protection circuit for a power converter with cascaded bipolar and/or unipolar semiconductors is provided. The protection circuit includes at least one comparator circuit which is adapted to monitor a voltage characteristic on a collector-emitter path of at least one semiconductor which is arranged in a polarity selection stage of the power converter and/or to monitor a voltage characteristic on at least one capacitor, which is arranged in the power converter. The at least one comparator circuit is further adapted to output an electrical signal, representing the voltage characteristic of the semiconductor and/or the at least one capacitor to at least one evaluation unit. The at least one evaluation unit is further adapted to evaluate the result from the at least one comparator circuit and to deactivate the semiconductors in case that the voltage characteristic of the semiconductors and/or the capacitors deviate from a predetermined threshold.

A protection circuit for a power converter with cascaded bipolar and/or unipolar semiconductors is provided. The protection circuit includes at least one comparator circuit which is adapted to monitor a voltage characteristic on a collector-emitter path of at least one semiconductor which is arranged in a polarity selection stage of the power converter and/or to monitor a voltage characteristic on at least one capacitor, which is arranged in the power converter. The at least one comparator circuit is further adapted to output an electrical signal, representing the voltage characteristic of the semiconductor and/or the at least one capacitor to at least one evaluation unit. The at least one evaluation unit is further adapted to evaluate the result from the at least one comparator circuit and to deactivate the semiconductors in case that the voltage characteristic of the semiconductors and/or the capacitors deviate from a predetermined threshold.

A power conversion device according to an embodiment includes a cell, a first sensor, a second sensor, a storage, a first controller, and a second controller. The first controller is configured to control or protect the cell on the basis of at least one of an output result of the first sensor and an output result of the second sensor. The second controller, in a case in which a change in at least one of the output result of the first sensor and the output result of the second sensor satisfies a first condition, is configured to execute at least one of a first operation of storing the output result of the first sensor in the storage, a second operation of storing the output result of the first sensor in the storage over a second period longer than a first period, and a third operation of storing the output result of the second sensor instead of the output result of the first sensor.

A power conversion device according to an embodiment includes a cell, a first sensor, a second sensor, a storage, a first controller, and a second controller. The first controller is configured to control or protect the cell on the basis of at least one of an output result of the first sensor and an output result of the second sensor. The second controller, in a case in which a change in at least one of the output result of the first sensor and the output result of the second sensor satisfies a first condition, is configured to execute at least one of a first operation of storing the output result of the first sensor in the storage, a second operation of storing the output result of the first sensor in the storage over a second period longer than a first period, and a third operation of storing the output result of the second sensor instead of the output result of the first sensor.