A three-level inverter includes controllable switch components T1 to T6. Each of the controllable switch components includes a parallel connected junction capacitor and an anti-parallel connected diode. A first terminal of T1 is connected to a positive direct current bus, a second terminal of T4 is connected to a negative direct current bus, a second terminal of T1 is connected to first terminals of T2 and T5. A controller is configured to: in a positive half cycle, control T3 to be conducted after T1 is conducted, and control T3 to be disconnected before T1 is conducted next time; and in a negative half cycle, control T2 to be conducted after T4 is conducted, and control T2 to be disconnected before T4 is conducted next time. The three-level inverter can balance voltages of the controllable switch components.

A power converter includes a PCB having opposing first and second sides, and a plurality of first commutation units and first capacitor unit disposed on the PCB. Each first commutation unit includes a first discrete component and a second discrete component. The second end of the first discrete component is electrically coupled to the first end of the second discrete component, and the first capacitor unit is electrically coupled to the first ends of the first discrete components and the second ends of the second discrete components in the plurality of first commutation units, respectively. The first discrete components and the second discrete components in the plurality of first commutation units are arranged in a row. The first discrete component and the second discrete component in each first commutation unit form a commutation loop together with the first capacitor unit.

A method for operating a multi-level bridge power converter includes providing a plurality of switching devices of the power converter in one of a neutral point clamped topology or an active neutral point clamped topology. The method also includes providing a plurality of deadtimes for the switching devices. Further, the method includes selecting one of the deadtimes for each of the switching devices such that at least two of the switching devices operate according to different deadtimes. Moreover, the method includes operating the switching devices at the selected deadtimes to allow a first group of the switching devices to switch slower than a second group of the switching devices such that the first group of the switching devices satisfy safe operating requirements while the second group of the switching devices switch faster than the first group.

A method for operating a multi-level bridge power converter includes providing a plurality of switching devices of the power converter in one of a neutral point clamped topology or an active neutral point clamped topology. The method also includes providing a plurality of deadtimes for the switching devices. Further, the method includes selecting one of the deadtimes for each of the switching devices such that at least two of the switching devices operate according to different deadtimes. Moreover, the method includes operating the switching devices at the selected deadtimes to allow a first group of the switching devices to switch slower than a second group of the switching devices such that the first group of the switching devices satisfy safe operating requirements while the second group of the switching devices switch faster than the first group.

In a vehicle drive system using a motor for cruising, the connection node of serially-connected first and second batteries is grounded. The operation of an inverter is controlled so that the motor drive voltage is higher than the output voltage of each of the first and second batteries. A battery unit is configured so that third and fourth batteries each in a form of a cartridge are removably loaded, and the loaded third battery is connected in parallel with the first battery and the loaded fourth battery is connected in parallel with the second battery.

An object is to provide a technique capable of improving the power efficiency of a semiconductor device. The semiconductor device includes first to sixth parallel connection bodies, each including a semiconductor switching element and a diode connected in antiparallel to the semiconductor switching element. At least one of the voltage drops of the second parallel connection body and the third parallel connection body is smaller than a voltage drop of at least one of the first parallel connection body, the fourth parallel connection body, the fifth parallel connection body, and the sixth parallel connection body.

An object is to provide a technique capable of improving the power efficiency of a semiconductor device. The semiconductor device includes first to sixth parallel connection bodies, each including a semiconductor switching element and a diode connected in antiparallel to the semiconductor switching element. At least one of the voltage drops of the second parallel connection body and the third parallel connection body is smaller than a voltage drop of at least one of the first parallel connection body, the fourth parallel connection body, the fifth parallel connection body, and the sixth parallel connection body.

An exemplary system includes an inverter coupled to a DC source, eight power switches and three DC-link capacitors that synthesize seven output voltage levels. In one example the inverter includes a four-level active neutral pointed clamped inverter (4L-ANCP) that includes six power switches of the eight power switches is operated at a switching frequency with a first voltage stress level, and a half-bridge that includes the other two of the eight power switches is coupled to the 4L-ANCP and operated at a fundamental frequency with a second voltage stress, the second voltage stress being higher than the first voltage stress level.

An exemplary system includes an inverter coupled to a DC source, eight power switches and three DC-link capacitors that synthesize seven output voltage levels. In one example the inverter includes a four-level active neutral pointed clamped inverter (4L-ANCP) that includes six power switches of the eight power switches is operated at a switching frequency with a first voltage stress level, and a half-bridge that includes the other two of the eight power switches is coupled to the 4L-ANCP and operated at a fundamental frequency with a second voltage stress, the second voltage stress being higher than the first voltage stress level.

An uninterruptible power supply (UPS) is provided that includes a split direct current (DC) link having a first capacitor coupled between a positive DC link terminal and a first node, and a second capacitor coupled between the first node and a negative DC link terminal. The UPS also includes a rectifier coupled to an input of the split DC link and a controller coupled to the rectifier. The rectifier includes first, second, and third legs, wherein each leg is configured to convert a first alternating current (AC) voltage received from an AC source into a DC voltage to be provided to the split DC link, and a fourth leg configured to balance DC link voltages of the first and second capacitors. The controller is configured to maintain functionality of the rectifier during at least one of a partial utility power outage, a full utility outage, and a failure of at least one of the first, second, third, and fourth legs.