A modular multilevel power converter includes first electric components on a first vehicle and second electric components on a second vehicle. The first vehicle and the second vehicle are placed at a spacing distance from each other. The first electric components and the second electric components are electrically interconnected by a plurality of first connecting conductors.

A system and method for controlling a DC midpoint terminal voltage of a three level inverter is provided. The method includes receiving an input power signal at a three level motor control system that includes a three level inverter, the three level inverter powering an electric motor, determining, in the three level motor control system, a speed value of the electric motor, and adjusting a zero-sequence inverter output voltage to adjust a midpoint voltage at the DC midpoint based on the determined speed value.

A system and method for controlling a DC midpoint terminal voltage of a three level inverter is provided. The method includes receiving an input power signal at a three level motor control system that includes a three level inverter, the three level inverter powering an electric motor, determining, in the three level motor control system, a speed value of the electric motor, and adjusting a zero-sequence inverter output voltage to adjust a midpoint voltage at the DC midpoint based on the determined speed value.

The present power conversion device includes an inverter, a step-up/down converter, a first capacitor, a second capacitor, a voltage sensor, a control device, and a backup power supply. The auxiliary device is connected between the first DC power supply and the step-up/down converter, and the control device includes an abnormality determination unit configured to determine that an abnormality has occurred when a control voltage is equal to or lower than a first threshold value, and a control unit configured to execute discharge control when the abnormality determination unit determines that the abnormality has occurred and an inter-terminal voltage measured by the voltage sensor is equal to or lower than a second threshold value.

The present power conversion device includes an inverter, a step-up/down converter, a first capacitor, a second capacitor, a voltage sensor, a control device, and a backup power supply. The auxiliary device is connected between the first DC power supply and the step-up/down converter, and the control device includes an abnormality determination unit configured to determine that an abnormality has occurred when a control voltage is equal to or lower than a first threshold value, and a control unit configured to execute discharge control when the abnormality determination unit determines that the abnormality has occurred and an inter-terminal voltage measured by the voltage sensor is equal to or lower than a second threshold value.

Provided is a snubber circuit comprising N parallel charging paths each having a positive-side capacitor, a first diode, and a negative-side capacitor sequentially connected in series between a positive-side terminal and a negative-side terminal, and configured to conduct current from the positive-side terminal toward the negative-side terminal; (N+1) parallel discharging paths each having a second diode connected between the negative-side terminal or the negative-side capacitor of k.sup.th charging path of N charging paths and the positive-side capacitor of (k+1).sup.th charging path of N charging paths or the positive-side terminal, and configured to counduct current from the negative-side terminal toward the positive-side terminal via at least one of the negative-side capacitor and the positive-side capacitor; and at least one auxiliary capacitor each being connected in parallel to at least one of the N first diodes included on N charging paths and (N+1) second diodes included on (N+1) discharging paths.

Provided is a snubber circuit comprising N parallel charging paths each having a positive-side capacitor, a first diode, and a negative-side capacitor sequentially connected in series between a positive-side terminal and a negative-side terminal, and configured to conduct current from the positive-side terminal toward the negative-side terminal; (N+1) parallel discharging paths each having a second diode connected between the negative-side terminal or the negative-side capacitor of k.sup.th charging path of N charging paths and the positive-side capacitor of (k+1).sup.th charging path of N charging paths or the positive-side terminal, and configured to counduct current from the negative-side terminal toward the positive-side terminal via at least one of the negative-side capacitor and the positive-side capacitor; and at least one auxiliary capacitor each being connected in parallel to at least one of the N first diodes included on N charging paths and (N+1) second diodes included on (N+1) discharging paths.

A method comprises during a first half cycle, configuring a first switch to operate as an always-on switch, turning on a second switch prior to turning on a third switch and turning off the third switch prior to turning off the second switch, wherein the first switch and the second switch are connected in series and further in parallel with the third switch between a first terminal of a power source and a filter and during a second half cycle, configuring a fourth switch to operate as an always-on switch, turning on a fifth switch prior to turning on a sixth switch and turning off the sixth switch prior to turning off the fifth switch, wherein the fourth switch and the fifth switch are connected in series and further in parallel with the sixth switch between a second terminal of the power source and the filter.

Offsetting or modulating the location of a gate between two transistors may achieve a lower power circuit and a higher speed circuit depending on the new location of the gate. In one example, a gate between a PFET transistor and an NFET transistor may be offset towards the PFET transistor to achieve a higher speed circuit than a conventional circuit with the gate located equal distance between the transistors. In another example, a gate between a PFET transistor and an NFET transistor may be offset towards the NFET transistor to achieve a lower power circuit than a conventional circuit with the gate located equal distance between the transistors.

Offsetting or modulating the location of a gate between two transistors may achieve a lower power circuit and a higher speed circuit depending on the new location of the gate. In one example, a gate between a PFET transistor and an NFET transistor may be offset towards the PFET transistor to achieve a higher speed circuit than a conventional circuit with the gate located equal distance between the transistors. In another example, a gate between a PFET transistor and an NFET transistor may be offset towards the NFET transistor to achieve a lower power circuit than a conventional circuit with the gate located equal distance between the transistors.