A drive circuit includes a first driver to control on/off of an upper arm, a second driver to control on/off of a lower arm, a first switching device including a first terminal connected with a power supply for the first driver, a second terminal connected with a power supply for the second driver and a control terminal, a booster circuit to turn on the first switching device by boosting a control signal which is at a high level when the lower arm is in an on state, a second switching device to cause continuity between the control terminal and the booster circuit when the control signal is at the high level, and first switch unit to short-circuit the control terminal and the terminal for grounding when the control signal is at the low level.

An array substrate has a display area and a bonding region. The display area includes a distal region, a proximal region, and a middle region therebetween. The array substrate includes a base, a common electrode located in the display area, a connecting lead disposed outside the distal region, a conductive frame at least partially surrounding the display area, and at least one first common signal line, at least one second common signal line and at least one third common signal line. The first common signal line, the second common signal line and the third common signal line are respectively coupled to portions of the common electrode located in the distal region, the proximal region and the middle region. The first common signal line is coupled to the connecting lead. The connecting lead and the portion of the common electrode located in the distal region are coupled to the conductive frame.

An array substrate has a display area and a bonding region. The display area includes a distal region, a proximal region, and a middle region therebetween. The array substrate includes a base, a common electrode located in the display area, a connecting lead disposed outside the distal region, a conductive frame at least partially surrounding the display area, and at least one first common signal line, at least one second common signal line and at least one third common signal line. The first common signal line, the second common signal line and the third common signal line are respectively coupled to portions of the common electrode located in the distal region, the proximal region and the middle region. The first common signal line is coupled to the connecting lead. The connecting lead and the portion of the common electrode located in the distal region are coupled to the conductive frame.

A method of protecting a converter of a wind turbine and a respective protection system are provided. The converter is coupled to a generator of the wind turbine to perform conversion of electrical power produced by the generator, the converter including plural semiconductor components that are operational to provide the conversion of the electrical power. The method includes the performing of a step of estimating a junction temperature of at least one of the semiconductor components by determining a current in the converter associated with power loss in one or more of the semiconductor components; estimating power loss associated with the one or more semiconductor components based on the determined current and on a state of the one or more semiconductor components; and using a thermal model to estimate the junction temperature of the semiconductor components based on the estimated power loss. The estimating step is repeatedly performed.

A method of protecting a converter of a wind turbine and a respective protection system are provided. The converter is coupled to a generator of the wind turbine to perform conversion of electrical power produced by the generator, the converter including plural semiconductor components that are operational to provide the conversion of the electrical power. The method includes the performing of a step of estimating a junction temperature of at least one of the semiconductor components by determining a current in the converter associated with power loss in one or more of the semiconductor components; estimating power loss associated with the one or more semiconductor components based on the determined current and on a state of the one or more semiconductor components; and using a thermal model to estimate the junction temperature of the semiconductor components based on the estimated power loss. The estimating step is repeatedly performed.

In accordance with at least one aspect of this disclosure, a method for pulse width modulation control includes resolving a reference vector for any number of active space vectors to determine a voltage offset for the reference vector, adding the voltage offset to each active vector to determine a modified modulated signal to be added to a carrier signal, and controlling, with a control module, a switching circuit based at least in part on the modified carrier signal.

In accordance with at least one aspect of this disclosure, a method for pulse width modulation control includes resolving a reference vector for any number of active space vectors to determine a voltage offset for the reference vector, adding the voltage offset to each active vector to determine a modified modulated signal to be added to a carrier signal, and controlling, with a control module, a switching circuit based at least in part on the modified carrier signal.

This application provides a photovoltaic system and a maximum power point tracking control method for a photovoltaic system. The photovoltaic system includes an MPPT controller and a power converter, and the MPPT controller is connected to the power converter. The MPPT controller is configured to: be connected to a photovoltaic array, and track a global maximum power point MPP of the photovoltaic array. The MPPT controller may be further configured to obtain, when there is a periodic shade for the photovoltaic array, a multi-peak search start moment of global MPPT of the photovoltaic array based on a status of tracking the global MPP of the photovoltaic array in a target time period, so that when the multi-peak search start moment in each MPPT period arrives, the global MPPT of the photovoltaic array is started, to output a working point of the global MPP of the photovoltaic array to the power converter. According to this application, efficiency of obtaining the working point of the global MPP of the photovoltaic array can be improved, and precision of controlling the global MPPT of the photovoltaic array can be improved.

This application provides a photovoltaic system and a maximum power point tracking control method for a photovoltaic system. The photovoltaic system includes an MPPT controller and a power converter, and the MPPT controller is connected to the power converter. The MPPT controller is configured to: be connected to a photovoltaic array, and track a global maximum power point MPP of the photovoltaic array. The MPPT controller may be further configured to obtain, when there is a periodic shade for the photovoltaic array, a multi-peak search start moment of global MPPT of the photovoltaic array based on a status of tracking the global MPP of the photovoltaic array in a target time period, so that when the multi-peak search start moment in each MPPT period arrives, the global MPPT of the photovoltaic array is started, to output a working point of the global MPP of the photovoltaic array to the power converter. According to this application, efficiency of obtaining the working point of the global MPP of the photovoltaic array can be improved, and precision of controlling the global MPPT of the photovoltaic array can be improved.

A microcontroller unit for controlling a three-level inverter including delayed fault protection is provided. The microcontroller unit includes an input port configured to receive a trip signal from a fault detection module, and a plurality of EPWM modules, each configured to control a power switch within the three-level inverter. The microcontroller unit includes an auxiliary EPWM module configured to receive the trip signal and produce a delayed trip signal, and processing circuitry coupled with the input port, the plurality of EPWM modules, and the auxiliary EPWM module. The processing circuitry is configured to, in response to activation of the trip signal, direct one of the plurality of EPWM modules to shut off its corresponding power switch upon activation of the trip signal, and to direct a different one of the plurality of EPWM modules to shut off its corresponding power switch upon activation of the delayed trip signal.