A power module including at least one substrate, a housing arranged on the at least one power substrate, a first terminal electrically connected to the at least one power substrate, a second terminal including a contact surface, a third terminal electrically connected to the at least one power substrate, a plurality of power devices arranged on and connected to the at least one power substrate, and the third terminal being electrically connected to at least one of the plurality of power devices. The power module further including a base plate and a plurality of pin fins arranged on the base plate and the plurality of pin fins configured to provide direct cooling for the power module.

A power module including at least one substrate, a housing arranged on the at least one power substrate, a first terminal electrically connected to the at least one power substrate, a second terminal including a contact surface, a third terminal electrically connected to the at least one power substrate, a plurality of power devices arranged on and connected to the at least one power substrate, and the third terminal being electrically connected to at least one of the plurality of power devices. The power module further including a base plate and a plurality of pin fins arranged on the base plate and the plurality of pin fins configured to provide direct cooling for the power module.

An object is to provide a technique capable of improving the power efficiency of a semiconductor device. The semiconductor device includes first to sixth parallel connection bodies, each including a semiconductor switching element and a diode connected in antiparallel to the semiconductor switching element. At least one of the voltage drops of the second parallel connection body and the third parallel connection body is smaller than a voltage drop of at least one of the first parallel connection body, the fourth parallel connection body, the fifth parallel connection body, and the sixth parallel connection body.

An object is to provide a technique capable of improving the power efficiency of a semiconductor device. The semiconductor device includes first to sixth parallel connection bodies, each including a semiconductor switching element and a diode connected in antiparallel to the semiconductor switching element. At least one of the voltage drops of the second parallel connection body and the third parallel connection body is smaller than a voltage drop of at least one of the first parallel connection body, the fourth parallel connection body, the fifth parallel connection body, and the sixth parallel connection body.

Converter device configured to convert direct voltage and current into alternating voltage and current to be supplied to a load (L). The converter device comprises a bank (11) of capacitors (12), a plurality of power semiconductors (13), a heat sink (14) and a casing (15).

Converter device configured to convert direct voltage and current into alternating voltage and current to be supplied to a load (L). The converter device comprises a bank (11) of capacitors (12), a plurality of power semiconductors (13), a heat sink (14) and a casing (15).

A motor driving system includes first and second motors including multiple first windings and second windings; a first inverter including a DC terminal connected to a DC voltage source and an AC terminal connected to the multiple first windings; a first switch part including a plurality of first mode change switches connected to the multiple first windings; a second inverter including a DC terminal connected to the DC voltage source and an AC terminal connected to the plurality of first mode change switches; a second switch part including a plurality of second mode change switches connected to the AC terminal of the second inverter and the multiple second windings; a third switch part including a plurality of third mode change switches connected to the multiple first windings; and a controller configured to control the short-circuited state or the open state of the multiple first mode, second and third mode change switches, based on whether the first and the second motors are driven.

A motor driving system includes first and second motors including multiple first windings and second windings; a first inverter including a DC terminal connected to a DC voltage source and an AC terminal connected to the multiple first windings; a first switch part including a plurality of first mode change switches connected to the multiple first windings; a second inverter including a DC terminal connected to the DC voltage source and an AC terminal connected to the plurality of first mode change switches; a second switch part including a plurality of second mode change switches connected to the AC terminal of the second inverter and the multiple second windings; a third switch part including a plurality of third mode change switches connected to the multiple first windings; and a controller configured to control the short-circuited state or the open state of the multiple first mode, second and third mode change switches, based on whether the first and the second motors are driven.

Provided is a reactor that can prevent a short circuit from occurring between turns of a coil even if a foreign object is present between turns. The reactor includes: an edgewise coil formed by a flat rectangular wire; a magnetic core; and a molded resin part that covers at least a portion of the magnetic core, wherein the edgewise coil includes a plurality of turns configured to form a rectangular shape, each of the plurality of turns includes four straight portions, and four curved corner portions that connect the adjacent straight portions to each other, each of the four corner portions includes an outer region in which a gap is provided between the adjacent turns, and the molded resin part is present in at least two of the gaps that are diagonally opposite to each other.

A conversion circuit includes a voltage supply circuit, a storage circuit, and a gate terminal. The storage circuit includes a first terminal and a source terminal. The voltage supply circuit is configured to provide a bias voltage according to a power supply voltage. The first terminal is configured to receive a low voltage. The source terminal is configured to output a source voltage according to a storage voltage and the low voltage, wherein the storage circuit is configured to storage the storage voltage according to the bias voltage and the low voltage. The gate terminal is configured to output a gate voltage, wherein during a first period, the gate terminal is coupled to the first terminal, and the gate-source voltage can form a negative voltage.