A fast chirp Phase Locked Loop (70) with a boosted return time includes a Voltage Controlled Oscillator, VCO, (12) generating a Frequency Modulated Continuous Waveform, FMCW, (14). The VCO responds to a filtered output voltage (74) of a filter (72) connected to a charge pump (28). A digital controller (82) modifies the FMCW to generate a chirp phase (304) and a return phase (300). The chirp phase includes a first linear change of the FMCW from a start frequency (202) to a stop frequency (204). The return phase includes a second linear change of the FMCW from the stop frequency to the start frequency. A boost circuit (86) connects to the digital controller and the filter. The boost circuit supplies a boost current (98) during the return phase. The boost current is proportional to a return slope of the return phase and inversely proportional to a VCO gain of the VCO.

A fast chirp Phase Locked Loop (70) with a phase preset includes a Voltage Controlled Oscillator, VCO, (12) generating a Frequency Modulated Continuous Waveform, FMCW, (14). The VCO responds to a filtered output voltage (74) of a filter (72) connected to a charge pump (28). A digital controller (82) modifies the FMCW to generate a chirp phase (304) and a return phase (300). The chirp phase includes a first linear change of the FMCW from a start frequency (202) to a stop frequency (204). The return phase includes a second linear change of the FMCW from the stop frequency to the start frequency. A phase preset circuit (86) connects to the digital controller and the filter. The phase preset circuit supplies a phase preset current (98) during a start frequency time (302) preceding the chirp phase. The phase preset current is proportional to a VCO gain of the VCO and inversely proportional to a chirp current during the chirp phase.

An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.

A chirp-generator comprising a phase-detector for providing a phase-difference-signal representative of a phase difference between a clock-input-signal and a feedback-signal. A VCO-circuit is configured to provide a chirp-generator-output-signal based on the phase-difference-signal. The VCO-circuit comprises a switched-varactor-bank, which includes a plurality of varactors, and a varactor-switch associated with each of the plurality of varactors. The varactor-switch is configured to selectively control whether or not the associated varactor contributes to the capacitance of the VCO-circuit, based on the state of a varactor-control-signal. The chirp-generator also includes a feedback-component configured to: receive the chirp-generator-output-signal; and apply a variable-multiplication-factor to the chirp-generator-output-signal in order to provide the feedback signal for the phase-detector. A controller provides a sequence of different variable-multiplication-factors to the feedback-component; and provides varactor-control-signals to the plurality of varactors such that the varactors are sequentially controlled such that they contribute to the capacitance of the VCO-circuit.

This disclosure relates to fractional-N phase-locked loops. A digital filter can filter out quantization noise from a modulator. Separate paths can process an integer part associated with an output signal of the digital filter and a fractional part associated with the output signal of the digital filter. The separate paths can be combined in the fractional-N phase-locked loop, for example, as a weighted sum.

A synthesizer comprises a first two-point modulation phase locked loop, TPM PLL, circuit that receives a first reference clock signal at a first reference frequency and a feedback signal at a feedback frequency and generates a first chirp signal by applying a two-point modulation PLL on the first reference clock signal, a second integer-n TPM PLL circuit that receives a second reference clock signal at a second reference frequency lower than the first reference frequency and generates a second chirp signal by applying a TPM PLL on the second reference clock signal, a mixer that downconverts the first chirp signal by the second chirp signal to obtain the feedback signal at the feedback frequency corresponding to the difference of the frequency of the first chirp signal and the second chirp signal, and a feedback path that feeds back the feedback signal to the first TPM PLL circuit.

A circuit includes an RF oscillator coupled in a phase-locked loop. The phase-locked loop is configured to receive a digital input signal, which is a sequence of digital words, and to generate a feedback signal for the RF oscillator based on the digital input signal. The circuit further includes a digital-to-analog conversion unit that includes a pre-processing stage configured to pre-process the sequence of digital words and a digital-to-analog-converter configured to convert the pre-processed sequence of digital words into the analog output signal. The circuit includes circuitry configured to combine the analog output signal and the feedback signal to generate a control signal for the RF oscillator. The pre-processing stage includes a word-length adaption unit configured to reduce the word-lengths of the digital words and a sigma-delta modulator coupled to the word-length adaption unit downstream thereof and configured to modulate the sequence of digital words having reduced word-lengths.

A spread spectrum clock generation apparatus includes a frequency modulator configured to generate an output clock signal, a frequency of which is variable with reference to a predetermined center frequency, by frequency-modulating an input clock signal according to a modulation profile signal; and a profile generator configured to generate a nested-modulation profile for controlling the frequency of the output clock signal, generate the modulation profile signal according to the nested-modulation profile, and output the modulation profile signal to the frequency modulator, wherein the profile generator is further configured to generate the nested-modulation profile by varying a cycle and a change range of a triangle modulation profile having a triangle waveform pattern having a pre-designated cycle and a pre-designated amplitude with reference to the center frequency in a time-frequency domain.

A frequency divider unit has a digital frequency divider configured to divide by an odd integer, and a dual-edge-triggered one-shot coupled to double frequency of an output of the digital frequency divider. The frequency divider unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, and 3.5. In embodiments, the frequency divider unit relies on circuit delays to determine an output pulsewidth, and in other embodiments the output pulsewidth is determined from a clock signal. In embodiments, the unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, and 7.5 as well as many integer ratios including 2, 4, 6, and 8. In embodiments, the digital frequency divider is configurable to provide a 50% duty cycle to the one-shot.

A modulation circuit includes a locked loop circuit with two-point modulation control and a phase-frequency detector configured to compare a reference frequency signal with a feedback frequency signal. A two-point modulation control circuit includes a first modulation path having a controllable gain and coupled to one of the first and second modulation control points and a second modulation path coupled to another of the first and second modulation control points. Gain matching of the first and second modulation paths is accomplished through the operation of a calibration circuit. The calibration circuit includes a phase detector circuit configured to compare the reference frequency signal with the feedback frequency signal to generate a phase detect signal, and a gain control circuit configured to adjust the controllable gain of the first modulation path as a function a correlation of the phase detect signal with signs of the modulation data.