An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.

A method of a control circuit of a communication device comprises: receiving a data signal to generate a phase data signal to a digital phase-locked loop (DPLL); using the DPLL to receive the phase data signal, to dynamically lock a particular clock, and to generate a phase modulation signal based on the phase data signal; and determining or adjusting an equivalent capacitance of an inter-stage circuit which is coupled between the DPLL and a power amplifier and configured for processing the phase modulation signal and generating a processed phase modulation signal to the power amplifier.

This disclosure relates to fractional-N phase-locked loops. A digital filter can filter out quantization noise from a modulator. Separate paths can process an integer part associated with an output signal of the digital filter and a fractional part associated with the output signal of the digital filter. The separate paths can be combined in the fractional-N phase-locked loop, for example, as a weighted sum.

A frequency divider unit has a digital frequency divider configured to divide by an odd integer, and a dual-edge-triggered one-shot coupled to double frequency of an output of the digital frequency divider. The frequency divider unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, and 3.5. In embodiments, the frequency divider unit relies on circuit delays to determine an output pulsewidth, and in other embodiments the output pulsewidth is determined from a clock signal. In embodiments, the unit is configurable to divide an input frequency by a configurable ratio selectable from at least non-integer ratios of 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, and 7.5 as well as many integer ratios including 2, 4, 6, and 8. In embodiments, the digital frequency divider is configurable to provide a 50% duty cycle to the one-shot.

A device of one aspect of the present invention includes a receiver to receive a modulation signal that has been subjected to frequency shift keying division ratio. The receiver includes a first demodulator and a demodulation control signal generator. The demodulation control signal generator includes a first frequency divider, a frequency control signal generator, and an oscillator. The first frequency divider divides a frequency of one of the modulation signal and the demodulation control signal by a first or second reception division ratio. The frequency control signal generator generates a frequency control signal based on a frequency of the other of the modulation signal and the demodulation control signal, and a frequency of the one of the modulation signal and the demodulation control signal obtained by division by the first or second reception division ratio. The oscillator generates the demodulation control signal based on the frequency control signal.

A fractional-N frequency synthesizer comprising a multi-phase generator, a multi-path error phase generator; a current combiner; a loop filter connected to the current combiner; an oscillator (150) connected to the loop filter; a frequency divider (160); a SDM connected to both the frequency divider and the multi-phase generator, to generate variable division ratio.

Various methods provide for trimming the gain in a dual-port phase-locked loop (PLL) of a radio transceiver. Use is made of the radio's demodulator to perform modulation accuracy measurements, thereby reducing the cost and complexity of external test equipment.

A time to digital converter may include a synchronization block configured to output a voltage pulse with duration based on a time difference between a reference oscillating signal and an input oscillating signal; a charge pump arranged to receive the voltage pulse and to convert the voltage pulse into a current pulse; an integrator comprising an integrator capacitor, the integrator being configured to receive the current pulse and integrate the current pulse as a charge on the integrator capacitor, resulting in an integrator output voltage; and a successive approximation register configured to determine the integrator output voltage with respect to a reference voltage by adjusting the charge on the integrator capacitor so as to reduce the integrator output voltage to within a least significant bit (D0) of a reference voltage by successive approximation, and configured to output the determined integrator output voltage as a digital signal.

The invention disclosed a signal processing system and method thereof, applicable to an environment providing accurate output frequency. By using the signal processing system, the stable output voltage (AMP OUT) of the error amplifier is inputted to the input of the voltage controlled oscillator (VCO), the output frequency (Fvco) of the VCO is provided to the input of fractional-N frequency divider for digital division. The output of the fractional-N frequency divider (Fo) is provided to the input of the frequency to voltage converter for frequency/voltage conversion. Then, the low pass filter is used to filter out the ripple of the output voltage (V1) of the frequency to voltage converter and the trebling jitter of the output of the fractional-N frequency divider. The signal processing system of the present invention utilizes the voltage locked loop property and digital frequency division to achieve accurate frequency output.

The invention disclosed a signal processing system and method thereof, applicable to an environment providing accurate output frequency. By using the signal processing system, the stable output voltage (AMP OUT) of the error amplifier is inputted to the input of the voltage controlled oscillator (VCO), the output frequency (Fvco) of the VCO is provided to the input of fractional-N frequency divider for digital division. The output of the fractional-N frequency divider (Fo) is provided to the input of the frequency to voltage converter for frequency/voltage conversion. Then, the low pass filter is used to filter out the ripple of the output voltage (V1) of the frequency to voltage converter and the trebling jitter of the output of the fractional-N frequency divider. The signal processing system of the present invention utilizes the voltage locked loop property and digital frequency division to achieve accurate frequency output.