A solid state power amplifier uses a Doherty power amplifier that can be implemented as a monolithic microwave integrated circuit. By adjusting the DC bias of the amplifying stages in each branch of the Doherty amplifier, the output power, linearity, and DC power can be adjusted to provide a specified output, where the specification for the output can include the maintaining of desired DC power and linearity. The Doherty power amplifier can be used in a satellite payload or other application utilizing solid state power amplifiers, while providing the proper amount of RF output power and DC power. A single amplifier can have its bias levels adjusted for different output levels, helping to minimize the number of designs that are required for a given satellite payload, reducing the variety of parts in a satellite payload.

A source follower with an input node and an output node includes a first transistor, a second transistor, and a DC (Direct Current) tracking circuit. The first transistor has a control terminal, a first terminal coupled to a first node, and a second terminal coupled to a second node. The second transistor has a control terminal, a first terminal coupled to a ground voltage, and a second terminal coupled to the first node. The DC tracking circuit sets the second DC voltage at the second node to a specific level. The specific level is determined according to the first DC voltage at the first node. The output node of the source follower is coupled to the first node.

An envelope tracking (ET) power management circuit is provided. The ET power management circuit includes an amplifier circuit(s) configured to output a radio frequency (RF) signal at a defined power level corresponding to a direct current, an alternating current, and an ET modulated voltage received by the amplifier circuit(s). The ET power management circuit can operate in a high-power ET mode when the defined power level exceeds a defined power level threshold and the RF signal is modulated to include no more than a defined number of resource blocks. The ET power management includes two ET tracker circuitries each generating a respective ET modulated voltage and two charge pump circuitries each generating a respective current. In the high-power ET mode, both charge pump circuitries are activated to each provide a reduced current to the amplifier circuit, thus helping to reduce a footprint and cost of the ET power management circuit.

A Class-D amplifier includes a loop filter circuit, a comparator circuitry, an output circuitry, and a common-mode control circuitry. The loop filter circuit generates first and second signals according to input and output signals and adjusts common-mode levels of the first and second signals according to a first common-mode signal. The comparator circuitry respectively compares a ramp signal with the first and second signals to generate pulse signals, and a common-mode level of the ramp signal is set based on a second common-mode signal. The output circuitry is powered by a power supply voltage to generate the output signals according to the pulse signals. The common-mode control circuitry performs an AC-coupling operation on the power supply voltage to generate a noise signal and generate one of the first and second common-mode signals according to the noise signal and another one of the first and second common-mode signals.

A solid state power amplifier uses a Doherty power amplifier that can be implemented as a monolithic microwave integrated circuit. By adjusting the DC bias of the amplifying stages in each branch of the Doherty amplifier, the output power, linearity, and DC power can be adjusted to provide a specified output, where the specification for the output can include the maintaining of desired DC power and linearity. The Doherty power amplifier can be used in a satellite payload or other application utilizing solid state power amplifiers, while providing the proper amount of RF output power and DC power. A single amplifier can have its bias levels adjusted for different output levels, helping to minimize the number of designs that are required for a given satellite payload, reducing the variety of parts in a satellite payload.

An envelope tracking (ET) power management circuit is provided. The ET power management circuit includes an amplifier circuit(s) configured to output a radio frequency (RF) signal at a defined power level corresponding to a direct current, an alternating current, and an ET modulated voltage received by the amplifier circuit(s). The ET power management circuit can operate in a high-power ET mode when the defined power level exceeds a defined power level threshold and the RF signal is modulated to include no more than a defined number of resource blocks. The ET power management includes two ET tracker circuitries each generating a respective ET modulated voltage and two charge pump circuitries each generating a respective current. In the high-power ET mode, both charge pump circuitries are activated to each provide a reduced current to the amplifier circuit, thus helping to reduce a footprint and cost of the ET power management circuit.

Envelope trackers providing compensation for power amplifier output load variation are provided herein. In certain configurations, a radio frequency (RF) system includes an antenna, a power amplifier that receives a radio frequency signal and outputs an amplified radio frequency signal to the antenna, a plurality of detectors coupled to the power amplifier and operable to generate a plurality of detection signals, and an envelope tracker that controls a supply voltage of the power amplifier based on an envelope of the radio frequency signal. The envelope tracker processes the plurality of detection signals to generate a load variation detection signal indicating a change in an output load of the power amplifier arising from a change in a voltage standing wave ratio (VSWR) of the antenna. Additionally, the envelope tracker adjusts a gain of the power amplifier based on the load variation detection signal.

Use of a closed loop APC may involve a problem of cost and power consumption due to increased circuit scale. The semiconductor device includes a power amplifier that amplifies an output from a transmission circuit and a regulator that supplies power to the power amplifier. The regulator includes an operational amplifier comprising a loop gain control circuit and a loop gain control voltage generation circuit that supplies control voltage to the loop gain control circuit. The loop gain control voltage generation circuit minimizes a loop gain of the operational amplifier when starting up the regulator.

A bias generation method or apparatus defined by any one or any practical combination of numerous features that contribute to low noise and/or high efficiency biasing, including: having a charge pump control clock output with a waveform having limited harmonic content or distortion compared to a sine wave; having a ring oscillator to generating a charge pump clock that includes inverters current limited by cascode devices and achieves substantially rail-to-rail output amplitude; having a differential ring oscillator with optional startup and/or phase locking features to produce two phase outputs suitably matched and in adequate phase opposition; having a ring oscillator of less than five stages generating a charge pump clock; capacitively coupling the clock output(s) to some or all of the charge transfer capacitor switches; biasing an FET, which is capacitively coupled to a drive signal, to a bias voltage via an active bias resistor circuit that conducts between output terminals only during portions of a waveform appearing between the terminals, and/or wherein the bias voltage is generated by switching a small capacitance at cycles of said waveform. A threshold voltage bias voltage generation circuit may A charge pump for the bias generation may include a regulating feedback loop including an OTA that is also suitable for other uses, the OTA having a ratio-control input that controls a current mirror ratio in a differential amplifier over a continuous range, and optionally has differential outputs including an inverting output produced by a second differential amplifier that optionally includes a variable ratio current mirror controlled by the same ratio-control input. The ratio-control input may therefore control a common mode voltage of the differential outputs of the OTA. A control loop around the OTA may be configured to control the ratio of one or more variable ratio current mirrors, which may particularly control the output common mode voltage, and may control it such that the inverting output level tracks the non-inverting output level to cause the amplifier to function as a high-gain integrator.

An envelope tracking (ET) power management circuit is provided. The ET power management circuit includes an amplifier circuit(s) configured to output a radio frequency (RF) signal at a defined power level corresponding to a direct current, an alternating current, and an ET modulated voltage received by the amplifier circuit(s). The ET power management circuit can operate in a high-power ET mode when the defined power level exceeds a defined power level threshold and the RF signal is modulated to include no more than a defined number of resource blocks. The ET power management includes two ET tracker circuitries each generating a respective ET modulated voltage and two charge pump circuitries each generating a respective current. In the high-power ET mode, both charge pump circuitries are activated to each provide a reduced current to the amplifier circuit, thus helping to reduce a footprint and cost of the ET power management circuit.