Aspects of the description provide for a circuit. In some examples, the circuit includes a input pair of transistors, a bias transistor having a bias transistor gate, a bias transistor drain, and a bias transistor source, the bias transistor drain coupled to the input pair of transistors and the bias transistor source coupled to ground, and a resistor coupled between the bias transistor gate and the input pair of transistors.

The present disclosure discloses a sensing circuit and a source driver including the same, capable of decreasing influence on the performance of an integrator according to a panel load and reducing a chip area by excluding a feedback capacitor of the integrator. The sensing circuit may convert an input current, received from a display panel, into an output current having linearity and an amount of current smaller than the input current.

Aspects of the description provide for a circuit. In some examples, the circuit includes a input pair of transistors, a bias transistor having a bias transistor gate, a bias transistor drain, and a bias transistor source, the bias transistor drain coupled to the input pair of transistors and the bias transistor source coupled to ground, and a resistor coupled between the bias transistor gate and the input pair of transistors.

An apparatus and method for analog to digital conversion of analog input signals are disclosed herein. In some embodiments, an analog-to-digital (ADC) may comprise: a first successive approximation register (SAR) circuit comprising a fast SAR (FSAR) circuit and a residue digital-to-analog converter (RDAC) circuit and a residue amplifier circuit, coupled to the RDAC circuit, comprising an amplifier circuit that is configured to amplify a residual signal generated by the RDAC circuit, wherein the amplifier circuit comprises a deadzone control circuit and a first, second and third inverter stages, wherein the third stage is biased to operate in a sub-threshold region.

Disclosed is an amplifier having a high slew rate without increasing power consumption. The amplifier includes an input unit, a conversion unit, an amplification unit, a frequency compensation circuit, and a slew rate improvement circuit. Alternatively, the amplifier includes an input unit, a conversion unit, an amplification unit, a frequency compensation circuit, a first slew rate improvement circuit, and a second slew rate improvement circuit.

Disclosed is an amplifier capable of minimizing short-circuit current of an output stage of a buffer upon transition of an output voltage while having a high slew rate without increasing power consumption. The amplifier includes an input unit, a conversion unit, an amplification unit, a frequency compensation circuit, and a short-circuit current minimization circuit. Alternatively, the amplifier includes an input unit, a conversion unit, an amplification unit, a frequency compensation circuit, a short-circuit current minimization circuit, and a slew rate improvement circuit.

This application provides an operational amplifier that increases the stability and settling speed of a common-mode feedback circuit. The operational amplifier includes N stages of amplifiers connected in series and M common-mode feedback circuits, where N and M are integers, N≥3, and N≥M>1. An i.sup.th common-mode feedback circuit in the M common-mode feedback circuits is configured to: detect a common-mode output voltage of a (j+b).sup.th stage of amplifier, and regulate an electrical parameter of at least one of the j.sup.th stage of amplifier to the (j+b).sup.th stage of amplifier, to stabilize the common-mode output voltage of the (j+b).sup.th stage of amplifier. An M.sup.th common-mode feedback circuit is configured to detect and stabilize a common-mode output voltage of an N.sup.th stage of amplifier. Herein i, j, and b are integers, M≥i≥1, N≥j≥1, i≥j, j+b≤N, and b≥0.

An amplifier circuit including an input amplifier, an output amplifier and a diode device is provided. The output amplifier includes a PMOSFET and an NMOSFET. The PMOSFET has a gate electrode serving as a first input end and a drain coupled to an output end. The NMOSFET has a gate electrode serving as a second input end and a drain coupled to the output end. The output amplifier outputs an output voltage at the output end, and is coupled to the input amplifier via at least one of the first and second input ends. The diode device is coupled between the output end and the at least one of the first and second input ends of the output amplifier. When a voltage difference between the output end and the at least one of the first and second input ends of the output amplifier is greater than a barrier voltage of the diode device, the diode device is turned on, and an overshoot of the output voltage is reduced.

An amplifier includes an input circuit that amplifies a difference between a first input voltage and a second input voltage to generate a first current and a second current. A positive feedback circuit amplifies a difference between the first current and the second current to generate a third current and a fourth current and outputs a difference between the third current and the fourth current through an output node. A temperature compensation circuit adjusts an amplification factor of the positive feedback circuit in response to a change of temperature.

An output buffer circuit includes an operational amplifier configured to generate an amplifier output voltage signal based on an input voltage signal and on a compensation current, a slew rate compensating circuit configured to generate the compensation current to increase a slew rate of the amplifier output voltage signal based on a difference between the input voltage signal and a feedback voltage signal, an output path circuit connected between the operational amplifier and an output pad, the output path circuit configured to transfer the amplifier output voltage signal to generate a pad output voltage signal through the output pad, and a feedback path circuit, the feedback path circuit connected between the slew rate compensating circuit and a feedback input node that is on the output path circuit, the feedback path circuit configured to generate the feedback voltage signal.