Provided herein are amplifiers, such as buffers, with increased headroom. An amplifier stage includes a follower transistor and current source configured to receive a power supply voltage comprising an alternating current component and a direct current component. The alternating current component of the power supply voltage has substantially the same frequency and magnitude as the input signal received by the follower transistor. In radio frequency (RF) and intermediate frequency (IF) buffer applications, for example, the increased headroom can allow for linear buffering of an input signals with increased amplitude so that the output power one decibel (OP1dB) compression point can be increased.

A balanced differential transimpedance amplifier with a single-ended input operational over a wide variation in the dynamic range of input signals. A threshold circuit is employed to either or a combination of (1) generate a varying decision threshold to ensure a proper slicing over a wide range of input current signal levels; and (2) generate a bias current and voltage applied to an input of a transimpedance stage to cancel out a dependence of the transimpedance stage voltage input on input current signal levels.

A circuit (e.g., implemented as part of a controller area network (CAN) bus receiver includes a pre-amplifier stage having first and second outputs. The circuit also includes a comparator having first and second inputs. The first input is coupled to the first output of the pre-amplifier stage, and the second input is coupled to the second output of the pre-amplifier stage. The comparator includes an input differential transistor pair, a second pair of transistors coupled to the input differential transistor pair in a cascode configuration, and a push-pull output stage coupled to the second pair of transistors.

A differential amplifier includes a positive leg, a negative leg, and biasing circuitry. The positive leg includes at least one positive leg transistor, a first positive leg degeneration capacitor, and positive leg degeneration capacitor biasing circuitry configured to bias the first degeneration capacitor during a reset period. The negative leg includes at least one negative leg transistor, a negative leg degeneration capacitor, and negative leg degeneration capacitor biasing circuitry configured to bias the negative leg degeneration capacitor during the reset period. The biasing circuitry biases current of both the at least one positive leg transistor and the at least one negative leg transistor based on capacitance of the first positive leg degeneration capacitor, capacitance of the first negative leg degeneration capacitor, and a sampling time during an amplification period. The differential amplifier may be a stage amplifier in an Analog to Digital Converter (ADC).

An embodiment includes a track and hold amplifier device. A device may include an emitter follower transistor coupled to each of an input and an output. The device may also include a charging node coupled between the output and a voltage supply, wherein the charging node is also coupled to the input via the emitter follower transistor. Further, the device may include a cascode switch coupled to each of the input and the output. The cascode switch may be configured to cause the emitter follower transistor to operate in a conductive state and charge the charging node during a track mode. The cascode switch may also be configured to cause the emitter follower transistor to operate in a non-conductive state to isolate the charging node from the input during a hold mode. The cascode switch may include a MOS-HBT transistor combination operating in class AB mode.

Disclosed embodiments include a method for reducing amplifier offset drift comprised of receiving a first differential input signal at a first transistor base terminal and a second differential input signal at a second transistor base terminal, coupling the collector of the first transistor to the emitter of a third transistor and the emitter of the second transistor to the emitter of a fourth transistor, then coupling the base of the third transistor to the base of the fourth transistor. The method is also comprised of coupling the collector of the fourth transistor to an output terminal, generating a temperature dependent error correction current to minimize the difference in the amount of current flowing through the third transistor and the amount of current flowing through the fourth transistor, then injecting the error correction current into the emitter terminal of at least one of either the third transistor or the fourth transistor.

Embodiments of a passive buffer circuit and a wideband communication circuit that uses the passive buffer circuit are disclosed. In an embodiment, the passive buffer circuit includes buffer elements connected between input terminals and output terminals that are connected to input terminals of a communication component circuit with a plurality of input transistors. Each of the buffer elements provides a first path with a resistor and a second path with a series-connected capacitor and inductor. The passive buffer circuit further includes current sources connected between the output terminals and at least one fixed voltage and a feedback loop from the input transistors to the current sources to control direct current (DC) voltage at each of the input terminals of the communication component circuit. The feedback loop includes an error amplifier that controls the current sources based on voltages on the input transistors with respect to a reference voltage.

The invention discloses a broadband logarithmic detector with high dynamic range, comprising a low noise amplifier, a compensate detection unit, a current summation and driving unit, an N-stage clipper amplifier and an N-stage detection unit. The invention improves the detection sensibility of the overall detector by adding a low noise amplifier before the first-stage clipper amplifier and extends the dynamic detection range of the overall detector through combination of the low noise amplifier and the compensate detection unit.

Technologies are provided for variable gain amplifiers (VGAs). An example VGA includes a resistor ladder including resistor legs coupled to first and second resistors; first differential switches connected to the resistor ladder and second differential switches connected to output nodes, a transistor in each of the first differential switches being coupled to an first electrical line interconnecting the first resistors and a different transistor in each of the first differential switches being coupled to a second electrical line interconnecting the second resistors; third differential switches connected to the resistor ladder and fourth differential switches connected to the output nodes, a transistor in each of the third differential switches being coupled to the first electrical line and a different transistor in each of the fourth differential switches being coupled to the second electrical line; and a pair of transistors respectively connected to the first differential switches and the third differential switches.

In some embodiments, a compensated power detector can include a power detector that includes a first detection cell having a bias input and an output, and a second detection cell having a signal input, a bias input and an output. The power detector can further include an error amplifier having a first input coupled to the output of the first detection cell, and a second input for receiving a reference voltage. The error amplifier can be configured to provide an output voltage to each of the bias inputs of the first and second detection cells, such that an output of the second detection cell is representative of power of a radio-frequency signal received at the signal input with an adjustment for one or more non-signal effects as measured by the first detection cell and the error amplifier.