We disclose apparatus which may provide power amplification in millimeter-wave devices with reduced size and reduced power consumption, and methods of using such apparatus. One such apparatus comprises an input transformer; a first differential pair of injection transistors comprising a first transistor and a second transistor; a first back gate voltage source configured to provide a first back gate voltage to the first transistor; a second back gate voltage source configured to provide a second back gate voltage to the second transistor; a second differential pair of oscillator core transistors comprising a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor are cross-coupled; a third back gate voltage source configured to provide a third back gate voltage to the third transistor; a fourth back gate voltage source configured to provide a fourth back gate voltage to the fourth transistor; and an output transformer.

We disclose apparatus which may provide power amplification in millimeter-wave devices with reduced size and reduced power consumption, and methods of using such apparatus. One such apparatus comprises an input transformer; a first differential pair of injection transistors comprising a first transistor and a second transistor; a first back gate voltage source configured to provide a first back gate voltage to the first transistor; a second back gate voltage source configured to provide a second back gate voltage to the second transistor; a second differential pair of oscillator core transistors comprising a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor are cross-coupled; a third back gate voltage source configured to provide a third back gate voltage to the third transistor; a fourth back gate voltage source configured to provide a fourth back gate voltage to the fourth transistor; and an output transformer.

We disclose apparatus which may provide power amplification in millimeter-wave devices with reduced size and reduced power consumption, and methods of using such apparatus. One such apparatus comprises an input transformer; a first differential pair of injection transistors comprising a first transistor and a second transistor; a first back gate voltage source configured to provide a first back gate voltage to the first transistor; a second back gate voltage source configured to provide a second back gate voltage to the second transistor; a second differential pair of oscillator core transistors comprising a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor are cross-coupled; a third back gate voltage source configured to provide a third back gate voltage to the third transistor; a fourth back gate voltage source configured to provide a fourth back gate voltage to the fourth transistor; and an output transformer.

We disclose apparatus which may provide power amplification in millimeter-wave devices with reduced size and reduced power consumption, and methods of using such apparatus. One such apparatus comprises an input transformer; a first differential pair of injection transistors comprising a first transistor and a second transistor; a first back gate voltage source configured to provide a first back gate voltage to the first transistor; a second back gate voltage source configured to provide a second back gate voltage to the second transistor; a second differential pair of oscillator core transistors comprising a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor are cross-coupled; a third back gate voltage source configured to provide a third back gate voltage to the third transistor; a fourth back gate voltage source configured to provide a fourth back gate voltage to the fourth transistor; and an output transformer.

In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

An amplifier may include first and second terminals to receive first and second input signals and a differential amplifier providing differential amplification of the first and second input signals. The differential amplifier may include a first differential amplifier stage to receive the first input signal and a second differential amplifier stage to receive the second input signal. The amplifier may further include a first bias circuit to bias the first differential amplifier stage, where the first bias circuit is connected to the second input terminal to provide anti-phase bias control of the first differential amplifier stage. The amplifier may further include a second bias circuit to bias the second differential amplifier stage, where the second bias circuit is connected to the first input terminal to provide anti-phase bias control of the second differential amplifier stage.

In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

An amplifier includes first through sixth transistors. The first transistor is of a first polarity type and has a control terminal and first and second terminals. The second transistor is of a second polarity type and has a control terminal and first and second terminals. The third transistor is of the first polarity type and has a control terminal and first and second terminals. The second terminal of the third transistor is coupled to the first terminal of the second transistor. The fourth transistor is of the second polarity type and has a control terminal and first and second terminals. The first terminal of the fourth transistor is coupled to the second terminal of the second transistor. The fifth transistor has a control terminal coupled to the control terminal of the third transistor. A sixth transistor has a control terminal coupled to the control terminal of the fourth transistor.

Methods, apparatus, and systems are described to facilitate phase detection for data clock synchronization. An example phase detection circuitry includes an oscillator having an output; frequency adjuster circuitry having an input, a first output, and a second output, the input of the frequency adjuster circuitry coupled to the output of the oscillator; a clock buffer circuitry including: a first resistor having a first terminal and a second terminal; and a second resistor having a first terminal and a second terminal, the second terminal of the second resistor coupled to the first terminal of the first resistor; and a feedback amplifier having a first input, a second input, and an output, the first input of the feedback amplifier coupled to a second terminal of the first resistor and a first terminal of the second resistor.