In a semiconductor device according to an embodiment, a thickness of a semiconductor layer of an SOI substrate on which a field effect transistor constituting an analog circuit is formed is set to 2 nm or more and 24 nm or less.

The present invention relates to a sigma-delta analogue-to-digital converter. The sigma-delta analogue-to-digital converter comprises a transconductance stage having first, second and third terminals. A capacitor is connected in parallel at the third terminal. Further, the sigma-delta analogue-to-digital converter comprises a quantiser at the third terminal of the transconductance stage with feedback by a voltage digital-to-analogue converter for feeding back a feedback signal to one of the terminals of the transconductance stage.

A two-stage differential amplifier with cross-coupled compensation capacitors. The differential amplifier includes first amplifier circuitry receiving a differential input voltage and presenting first and second intermediate outputs. The amplifier further includes a second amplifier stage with a first leg having an input coupled to the second intermediate output of the first amplifier circuitry, and a second leg having an input coupled to the first intermediate output of the first amplifier circuitry. A compensation capacitor is provided for each leg of the second amplifier stage, each coupled between the output of that amplifier leg and its input. A first cross-coupled capacitor is coupled between the output of the first amplifier leg to the input of the second amplifier leg, and a second cross-coupled capacitor is coupled between the output of the second amplifier leg and the input of the first amplifier leg.

Amplifiers, amplification circuits, and phase shifters, for example, for flexibly adjusting an output phase to thereby meet a requirement of a constant phase on a link in a communications field, are provided. In one aspect, an amplifier includes first, second, and third MOS transistors. The first MOS transistor includes a gate separately coupled to a signal input end and a bias voltage input end, a source coupled to a power supply, and a drain separately coupled to sources of the second and third MOS transistors. A drain of the third MOS transistor is coupled to a ground, and a drain of the second MOS transistor is coupled to a signal output end. The bias voltage input end is configured to receive a bias voltage to adjust a phase difference between an input signal at the signal input end and an output signal at the signal output end.

An output gain of a latch circuit is increased. The latch circuit includes a first circuit, a second circuit, and first to fourth transistors. The latch circuit includes a first input/output terminal and a second input/output terminal. The first circuit and the second circuit have a function of a current source. In the case where the third transistor is off and the fourth transistor is on, the latch circuit is supplied with a first input signal supplied to the first input/output terminal and a second input signal supplied to the second input/output terminal. In the case where the third transistor is on and the fourth transistor is off, an inverted signal of the first input signal is output to the first input/output terminal of the latch circuit, and an inverted signal of the second input signal is output to the second input/output terminal of the latch circuit. The first circuit and the second circuit increase the output gain of the latch circuit.

Techniques for controlling a low-dropout (LDO) voltage regulator. In an example, an LDO voltage regulator circuit includes an amplifier having an output coupled to a transistor. First and second inputs of the amplifier are coupled to a power supply node via first and second resistors, respectively. The transistor gate is coupled to the amplifier output, the transistor source is coupled to the second input of the amplifier, and the transistor drain is coupled to a reference voltage node. The second resistor is variable based on the amplifier output and a reference voltage from the reference voltage node. In an example, the reference voltage node is connectable to ground via a reference resistor connected in parallel with a noise-filtering capacitor, which causes a reference current to flow through the transistor. The reference current is adjusted based on the drain-to-source voltage of the transistor.

An amplifier circuit comprises a multi-stage amplifier having a plurality of amplifiers cascaded between an input port V.sub.in and an output port V.sub.out to form a differential input stage and N subsequent gain stages, a capacitive load C.sub.L coupled to the output port V.sub.out, and a compensation network coupled to the multi-stage amplifier and configured for positioning Pole-Zero pairs of each stage of the multi-stage amplifier below a unity gain frequency ω.sub.t of the multi-stage amplifier when compensated, with Zeros positioned lower than Poles so as to increase the unity gain frequency ω.sub.t.

Apparatus and methods for envelope tracking systems with automatic mode selection are provided herein. In certain configurations, a power amplifier system includes a power amplifier configured to provide amplification to a radio frequency signal and to receive power from a power amplifier supply voltage, and an envelope tracker including a signal bandwidth detection circuit configured to generate a detected bandwidth signal based on processing an envelope signal corresponding to an envelope of the radio frequency signal. The envelope tracker further includes a switch bank configured to receive a plurality of regulated voltages, a filter configured to filter an output of the switch bank to generate the power amplifier supply voltage, and a mode control circuit configured to control a filtering characteristic of the filter based on the detected bandwidth signal.

An optical receiver disclosed includes a bias terminal, an input terminal, a photodiode, an amplifier circuit, a first resistor, a bypass circuit, a filter circuit, and a control circuit. The photodiode receives a bias from the filter circuit through the bias terminal, and outputs a current signal to the amplifier circuit through the input terminal. The amplifier circuit converts an input current to an output voltage. The bypass circuit electrically connected to the input terminal decreases a first input impedance viewed from the input terminal, when activated, and increases the first input impedance, when deactivated. The filter circuit increases a second input impedance viewed from the bias terminal, when a dumping function thereof is activated, and decreases the second input impedance, when the dumping function is deactivated. The control circuit activates the dumping function and the bypass circuit, when the output voltage is larger than a certain voltage.

In examples, a system includes a differential input device having a first input and a second input. The system includes a window generator configured to output, at a first output, a first voltage above a reference voltage and a second voltage, at a second output, below the reference voltage. The system includes a multiplexer coupled to the first output and the second output, the multiplexer configured to receive the first voltage, the second voltage, and an input voltage. The system includes a selector coupled to the multiplexer and configured to select the first voltage, the second voltage, or the input voltage based on a value of the input voltage, where the selector is configured to cause the multiplexer to provide the selected voltage to the first input of the differential input device, where a voltage source provides the reference voltage to the second input of the differential input device.