An operational amplifier and a differential amplifying circuit thereof. The differential amplifying circuit receives a differential input signal and outputs a differential output signal. The differential amplifying circuit includes an output port that has a first terminal and a second terminal, the differential output signal being outputted via the first and second terminals; a first transistor pair receiving the differential input signal via two first ends and coupling to the first and second terminals respectively via two second ends; a second transistor pair receiving the differential input signal via two first ends and coupling to the first and second terminals respectively via two second ends; and a third transistor pair receiving a control signal via two first ends and coupling to the first and second terminals respectively via two second ends. The control signal controls the third transistor pair to switch on or off and/or controls the current flowing therethrough.

In an output amplifier stage of an operational amplifier circuit, the first p-well of the first nMOSFET and the second p-well of the second nMOSFET are connected to the fourth node. Further, the first n-well of the first pMOSFET and the second n-well of the second pMOSFET are connected to the fifth node. At least one of the fourth node and the fifth node is connected to an output terminal VOUT.

In an example, a circuit includes a transistor and a first amplifier having an output coupled to a control terminal of the transistor. The circuit includes a second amplifier having a second amplifier output coupled to the control terminal of the transistor. The circuit includes a resistor-capacitor network. The circuit also includes a first switch coupled to the first amplifier output, the transistor, and the resistor-capacitor network. The circuit includes a second switch coupled to the second amplifier output, the transistor, and the resistor-capacitor network, where the first switch is configured to couple the first amplifier output to the resistor-capacitor network, and the second switch is configured to couple the second amplifier output to the resistor-capacitor network.

Methods and apparatus are disclosed for complex-zero equalizers. An example circuit comprises driver circuitry including a first input, and equalizer circuitry including a second input, a first output coupled to the first input, a transistor including a gate terminal, a drain terminal, and a source terminal, the gate terminal coupled to the second input and the drain terminal coupled to the first output, an inductor including a first inductor terminal and a second inductor terminal, the first inductor terminal coupled to the source terminal of the transistor, a resistor coupled to the second inductor terminal, and a capacitor including a first terminal and a second terminal coupled to the source terminal and to the first inductor terminal and the second terminal coupled to ground.

In an output amplifier stage of an operational amplifier circuit, the first p-well of the first nMOSFET and the second p-well of the second nMOSFET are connected to the fourth node. Further, the first n-well of the first pMOSFET and the second n-well of the second pMOSFET are connected to the fifth node. At least one of the fourth node and the fifth node is connected to an output terminal VOUT.

A calibration circuit includes a replica transconductance stage that is a replica of a transconductance amplifier in a serializer/deserializer (SerDes) interface and a replica transimpedance stage that is a replica of a transimpedance amplifier in the SerDes interface. The replica transimpedance stage has an input coupled to its output. A comparison circuit is configured to generate a difference signal representative of a difference between voltage levels of an input signal received at an input of the replica transconductance stage and an output signal representative of voltage level at the output of the replica transimpedance stage. Replica feedback resistors are configured to couple an output of the replica transimpedance stage to the input of the replica transconductance stage. The difference signal can be used to select resistance values provided by the replica feedback resistors and by corresponding gain control resistors in the transimpedance amplifier in the SerDes interface.

Amplifiers incorporating equalizer and bias offset correction circuits are described. An example amplifier circuit with equalizer and bias offset correction includes an amplifier with an input, an equalizer circuit coupled to the input of the amplifier, and a bias offset correction circuit coupled to the input of the amplifier. The bias offset correction circuit is configured to adjust a bias potential at the input of the amplifier. In one example, the amplifier is a differential amplifier with differential inputs, the equalizer circuit is coupled to the differential inputs of the amplifier and is configured to adjustably modify a gain of the amplifier over frequency, and the bias offset correction circuit is coupled to the differential inputs of the amplifier and is configured to compensate for modifications to bias potentials at the differential inputs of the amplifier due to operation of the equalizer circuit.