A fourth-order feedforward compensation operational amplifier is provided. The amplifier includes a first transconductance amplification unit, a second transconductance amplification unit, a third transconductance amplification unit, a fourth transconductance amplification unit, a fifth transconductance amplification unit, a sixth transconductance amplification unit, and a seventh transconductance amplification unit. The first unit, the second unit, the third unit, and the fourth unit are cascaded in sequence to form a fourth-order operational amplifier path. The first unit, the fifth unit, and the fourth unit form a third-order operational amplifier path. The first unit and the sixth unit form a second-order operational amplifier path. The seventh unit forms a first-order operational amplifier path. The first-order path performs feedforward compensation on the second-order path, the second-order path performs feedforward compensation on the third-order path, and the third-order path performs feedforward compensation on the fourth-order path.

A high speed internal hysteresis comparator is provided. Impedance supply units are disposed at control terminals of transistors of an active load of a differential amplifier of the high-speed hysteresis comparator, such that a gain when the transistors operate in an active region and a responding speed of the high-speed hysteresis comparator are increased.

In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

A switched-capacitor circuit is described herein. In accordance with one exemplary embodiment the switched-capacitor circuit includes a first input node and a second input node and an input switch unit. The input switch is connected to the first input node and the second input node and has a first output node and a second output node. A first capacitor is coupled to the first output node of the input switch unit, and a second capacitor is coupled to the second output node of the input switch unit. The input switch unit includes a plurality of switches configured to con-nect and disconnect one of the first and second input nodes and one of the first capacitor and the second capacitor. The input switch unit further includes a first charge pump coupled to the first input node and a second charge pump coupled to the second input node. The first charge pump is configured to generate, based on a clock signal, switching signals for a switch of the plurality of switches, and the second charge pump is configured to generate, based on the clock signal, switching signals for a further switch of the plurality of switches.

An amplifier includes an input circuit that amplifies a difference between a first input voltage and a second input voltage to generate a first current and a second current. A positive feedback circuit amplifies a difference between the first current and the second current to generate a third current and a fourth current and outputs a difference between the third current and the fourth current through an output node. A temperature compensation circuit adjusts an amplification factor of the positive feedback circuit in response to a change of temperature.

Certain aspects of the present disclosure generally relate to using cross-coupled transistors for source degeneration of an amplification stage. For example, the amplification stage generally includes a differential amplifier comprising transistors, cross-coupled transistors coupled to the differential amplifier, and an impedance coupled between drains of the cross-coupled transistors. In certain aspects, the differential amplifier comprises a push-pull amplifier, and the transistors of the push-pull amplifier comprise cascode-connected transistors.

An integrated circuit includes: an amplifier circuit including a first inverter and a second inverter to amplify a voltage difference between a first line and a second line; a replica amplifier circuit including a first replica inverter having an input terminal and an output terminal which are coupled to a second replica line and replicating the first inverter, and that includes a second replica inverter having an input terminal and an output terminal which are coupled to a first replica line and replicating the second inverter; and a current control circuit suitable for controlling an amount of a current sourced to the replica amplifier circuit and an amount of a current sunken from the replica amplifier circuit based on comparison of an average level between a voltage of the first replica line and a voltage of the second replica line with a level of a target voltage.

A ripple pre-amplification based fully integrated LDO pertains to the technical field of power management. The positive input terminal of a transconductance amplifier is connected to a reference voltage Vref, and the negative input terminal of the transconductance amplifier is connected to the feedback voltage V.sub.fb. The output terminal of the transconductance amplifier is connected to the negative input terminal of a transimpedance amplifier and the negative input terminal of an error amplifier. The positive input terminal of the transimpedance amplifier is connected to the ground GND, and the output terminal of the transimpedance amplifier is connected to the positive input terminal of the error amplifier. The gate terminal of the power transistor M.sub.P is connected to the output terminal of the error amplifier, the source terminal of the power transistor M.sub.P is connected to an input voltage V.sub.IN, and the drain terminal of the power transistor M.sub.P is grounded.

A load-modulated balanced amplifier (LMBA) based on a variable cross-coupled pair (XCP) is provided. The LMBA includes an adaptive bias (ADB) circuit, a first balance terminal amplifier module, a second balance terminal amplifier module, a control terminal amplifier module, a first driver amplifier module, a second driver amplifier module, a third driver amplifier module, a variable XCP, a resistor R5, a resistor R6, a 90-degree differential coupler Q1, a 90-degree differential coupler Q2, and a 90-degree differential coupler Q3.

Apparatuses, systems, and methods for compensated sense amplifier with cross-coupled n-type transistors. A sense amplifier has a pair of p-type transistors coupled between a system voltage and respective first and second gut nodes. When a command signal is active, the p-type transistors are coupled in a diode fashion from the system voltage to the respective gut nodes. The amplifier also has a pair of n-type transistors which are cross coupled, where a first n-type transistor has a node coupled to the first gut node and a gate coupled to the second gut node and the second n-type transistor has a node coupled to the second gut node and a gate coupled to the first gut node. Each of the n-type transistors may have a separate current flowing through them and respective one of a pair of feedback transistors to a ground voltage.