Differential switching output stage for audio, power and digital data transmission can cause a common mode error due to asymmetric transition between positive and negative outputs. Systems and methods are provided for common mode error correction. In particular, summing nodes, novel error amps an edge switching can be used for common-mode feedback (CMFB) in differential signaling and other applications.

A digitally controlled grounded capacitor multiplier includes: a single capacitor directly connected at one end to an input voltage and at another end to a negative input of an operational amplifier; the operational amplifier including a negative feedback loop; and a digitally controlled current amplifier (DCCA) connected to an output of the operational amplifier. The DCCA digitally controls the digitally controlled grounded capacitor multiplier. The digitally controlled grounded capacitor multiplier comprises only two active devices consisting of the operational amplifier and the DCCA.

There is provided a device that includes a MOS transistor and a bias circuit coupled to the MOS transistor. The bias circuit is configured to bias the MOS transistor thereby maintaining the MOS transistor outside of saturation. The MOS transistor is configured to operate as a buffer or an amplifier, while being outside of saturation.

A circuit includes first through fourth transistors and a device. The first transistor has a control input and first and second current terminals. The control input provides a first input to the circuit. The second transistor has a control input and first and second current terminals. The control input provides a second input to the circuit. The third transistor has a control input and first and second current terminals. The fourth transistor has a control input and first and second current terminals. The second current terminal of the fourth transistor is coupled to the second current terminal of the third transistor, and the control input of the fourth transistor is coupled to the first current terminals of the first and second transistors. The device is configured to provide a fixed voltage to the control input of the third transistor.

A comparator having: a first transistor coupled to a first input terminal; a first current source coupled to the first transistor; a second transistor coupled to a second input terminal and coupled to the first current source; a third transistor coupled in series with the first transistor; a fourth transistor coupled in series with the second transistor; a fifth transistor coupled in series with the first transistor; a sixth transistor coupled in series with the second transistor; a seventh transistor coupled to the first input terminal and coupled as a source follower to the fifth transistor; and an eighth transistor coupled to the second input terminal and coupled as a source follower to the sixth transistor. The comparator also including a differential amplifier coupled to the first output terminal and coupled to the second output terminal.

Storage devices are capable of utilizing receiver devices with native devices configured to support lower voltage supplies for higher read performances. The receiver device may include a current source circuit, first and second stage circuits, and a duty cycle balancer circuit. The first stage circuit may utilize first and second native devices with a threshold voltage (VTH) that enables proper lower voltage operations in saturation at high speeds. The current source stage circuit may utilize a third native device to track a transconductance and provide a reference current that becomes proportional to VTH to maintain tighter gain across process, variation, and temperature (PVT). The second stage circuit may utilize a current folding stage to provide a high gain for faster conversion of intermediate signals. The duty cycle balancer may utilize a fourth native device to balance a rise and fall delay skew across the PVT to maintain tighter duty cycle.

An amplifier with an input stage comprising: a first current mirror; a first input differential pair; a first current source; a second current source; a second input differential pair, wherein the first input differential pair and the second input differential pair receive a reference voltage; a second current mirror; and a voltage control transmission circuit. An extra current path in the first current mirror is formed and a current flowing through the extra current path flows through the second current mirror to a ground when the reference voltage is higher than a first predetermined value. Also, an extra current path in the second current mirror is formed and a current flowing through the extra current path in the second current mirror flows to the first current mirror when the reference voltage is lower than a second predetermined value.

A headphone driver is used to drive a headphone apparatus, which includes a first differential driver, a first positive output terminal, a first negative output terminal, and a second negative output terminal. The first positive output terminal is connected to the first terminal. A switch unit is disposed on a feedback path at the first negative output terminal and the second negative output terminal, to enable the first/second negative output terminal in feedback as a close loop to output to the third/fourth terminal and disable the second/first negative output terminal at a first/second operation state. The first differential driver includes a first positive voltage driving circuit, a first negative voltage driving circuit, and a second negative voltage driving circuit, respectively providing the first positive output terminal, the first negative output terminal, and the second negative output terminal.

This application provides an operational amplifier and a start-up circuit of the operational amplifier. The start-up circuit has advantages of simple structure and low power consumption. The operational amplifier includes a multi-stage amplifier and a start-up circuit, where the start-up circuit includes: a first start-up transistor M16 and a second start-up transistor M17, a source of the first start-up transistor M16 and a source of the second start-up transistor M17 are connected to a tail bias node of a first-stage amplifier in the multi-stage amplifier, a gate of the first start-up transistor M16 and a gate of the second start-up transistor M17 are configured to connect to a first bias voltage V.sub.b, and a drain of the first start-up transistor M16 and a drain of the second start-up transistor M17 are connected to input terminals of a second-stage or higher-stage amplifier.

A circuit for startup of a multi-stage amplifier circuit includes a pair of input nodes and at least two output nodes configured to be coupled to a multi-stage amplifier circuit. A startup differential stage includes a differential pair of transistors having respective control terminals coupled to the pair of input nodes, and each transistor in the differential pair of transistors has a respective current path therethrough between a respective output node and a common source terminal. The startup differential stage is configured to sense a common mode voltage drop at a first differential stage of the multi-stage amplifier circuit. Current mirror circuitry includes a plurality of transistors coupled to the common terminal of the differential pair of transistors and coupled to two output nodes of the at least two output nodes.