An operational amplifier includes a first transistor, a second transistor, a third transistor, a first constant current source, an output state, a first switch, and a second switch. The first transistor has a first gate configured to receive an output voltage from an output node. The second transistor has a second gate. The third transistor has a third gate configured to receive an input voltage. The first constant current source is coupled to sources of the first transistor, the second transistor, and the third transistor. The output stage is configured to drive the output voltage on the output node based on a first current through the first transistor, a second current through the second transistor, and a third current through the third transistor. The first switch is coupled between the second gate of the second transistor and the third gate of the third transistor; and the second switch is coupled between the output node and the second gate of the second transistor.

A linear power supply circuit, includes: output transistor between input terminal where input voltage is applied and output terminal where output voltage is applied; a driver driving the output transistor based on difference between voltage based on the output voltage and reference voltage; and phase compensation circuit, wherein the driver includes differential amplifier outputting voltage corresponding to the difference between the voltage based on the output voltage and the reference voltage, a first capacitance having one end where output of the differential amplifier is applied and the other end where ground potential is applied, a converter converting the voltage based on the output of the differential amplifier into current, and a current amplifier amplifying the current output from the converter, and wherein the phase compensation circuit lowers gain of transfer function of the linear power supply circuit and output capacitor connected to the output terminal.

A phased array receiver can include a plurality of antennas, a plurality of compound analog-to-digital converters and a beam former. The plurality of antennas can be arranged in an array. The plurality of compound analog-to-digital converters can include respective inputs coupled to respective ones of the plurality of antennas. Respective output of the plurality of compound analog-to-digital converters can be coupled to the beam former. Each compound analog-to-digital converter can include a plurality of time interleaved sub-analog-to-digital converters. Sampling by the sub-analog-to-digital converters can be random between the sub-analog-to-digital converters within respective compound analog-to-digital converters and random between the plurality of compound analog-to-digital converters. In addition, dynamic element mismatch using a random bitstream generator can be employed in digital-to-analog converters and analog-to-digital converters.

Provided is a probe which transmits an ultrasonic wave to a diagnostic site and receives a reception signal which is a reflected wave. The probe includes: a plurality of transducers; a plurality of low-noise amplifying circuits respectively corresponding to the plurality of transducers; and a single differential converter which converts a control signal rising with the elapse of time to a first bias signal rising with the elapse of time and a second bias signal falling with the elapse of time to control the plurality of low-noise amplifying circuits, and the low-noise amplifying circuit includes an attenuator which attenuates: an electric signal from the transducer; a first amplifying circuit which sets the first bias signal as a bias and amplifies an output signal of the attenuator to be gradually increased with the elapse of time; a second amplifying circuit which sets the second bias signal as a bias and amplifies the output signal of the attenuator to be gradually reduced with the elapse of time; and a subtractor which subtracts an output of the first amplifying circuit and an output of the second amplifying circuit.

A device is disclosed. The device includes an operational amplifier, an output circuit and a first feedback circuit. The operational amplifier includes an input terminal that is configured to receive a feedback signal. The output circuit is coupled to an output terminal of the operational amplifier and is configured to generate an output signal in response to an output of the operational amplifier. The first feedback circuit is coupled to the output circuit and is configured to couple at least one first ripple signal in the output signal to the input terminal of the operational amplifier that is configured to receive the feedback signal, for adjusting the output signal. A method also is disclosed herein.

An amplifier circuit comprises a first unit circuit and a second unit circuit. The first unit circuit may include a first current mirror circuit that includes a first active inductor including a P-channel transistor, and a first input circuit configured to generate a first differential current and a second differential current based on a pair of differential input signals. The second unit circuit may include a second current mirror circuit that includes a second active inductor including a P-channel transistor, and a second input circuit configured to generate a third differential current and a fourth differential current based on the pair of differential input signals.

The physically unclonable function device (DIS) comprises a set of MOS transistors (TR1i, TR2j) mounted in diodes having a random distribution of respective threshold voltages, and comprising N first transistors and at least one second transistor. At least one output node of the function is capable of delivering a signal, the level of which depends on the comparison between a current obtained using a current circulating in the at least one second transistor and a current obtained using a reference current that is equal or substantially equal to the average of the currents circulating in the N first transistors. A first means (FM1i) is configured to impose on each first transistor a respective fixed gate voltage regardless of the value of the current circulating in the first transistor, and a second means (SM2j) is configured to impose a respective fixed gate voltage on each second transistor regardless of the value of the current circulating in the second transistor.

This disclosure relates to an output buffer including an input stage configured to monitor a difference between an input voltage and an output voltage, a current summing stage configured to generate amplified currents and control voltages according to the difference between the input voltage and the output voltage monitored by the input stage, an output stage configured to perform a pull-up operation or a pull-down operation according to the control voltages output from the current summing stage to generate the output voltage at an output terminal, and a slew boost circuit configured to perform a slew boost operation of adjusting some currents among currents provided from the current summing stage to the input stage according to the difference between the input voltage and the output voltage by monitoring the difference between the input voltage and the output voltage and selectively perform the slew boost operation by monitoring the control voltages.

A digital-to-analog conversion circuit includes: a decoder that, if set to a first selection state, selects two different reference voltages from a reference voltage group on the basis of a digital data signal and outputs the two reference voltages as first and second selection voltages, and if set to a second selection state, selects two reference voltages from the reference voltage group in a manner allowing redundancy and outputs the two reference voltages as the first and second selection voltages; and an amplifier circuit that amplifies and outputs a voltage obtained by averaging a combination of the first and second selection voltages with weighting factors set in advance.

The present disclosure discloses a sensing circuit and a source driver including the same, capable of decreasing influence on the performance of an integrator according to a panel load and reducing a chip area by excluding a feedback capacitor of the integrator. The sensing circuit may convert an input current, received from a display panel, into an output current having linearity and an amount of current smaller than the input current.