An arithmetic circuit includes an auto-zero amplification circuit that compensates an offset of an entered differential signal, and a comparator circuit that converts an output signal from the auto-zero amplification circuit to a digital signal. The auto-zero amplification circuit and comparator circuit are provided in the same package.

A Gated CDS Integrator (GCI) may amplify low-level signals without introducing excessive offset and noise. The GCI may also amplify the low level signals with accurate and variable gain. The GCI may include a modulator preceding an amplifier such that offset or noise present in a signal path between the modulator and a demodulator input is translated to a higher out of band frequency, and thereafter reduced by a double sampled discrete time integrator which also reduces thermal noise. The thermal noise may also be reduced by averaging the output of the discrete time integrator.

A Gated CDS Integrator (GCI) may amplify low-level signals without introducing excessive offset and noise. The GCI may also amplify the low level signals with accurate and variable gain. The GCI may include a modulator preceding a linear amplifier such that offset or noise present in a signal path between the modulator and a demodulator input is translated to a higher out of band frequency.

An analog signal path portion of a signal path may have: (i) an audio input for receiving an analog signal, an audio output for providing an output signal, and a selectable analog gain, and may be configured to generate the output signal based on the analog signal and in conformity with the selectable analog gain; and (ii) a digital path portion having a selectable digital gain and configured to receive a digital input signal and convert the digital input signal into the analog signal in conformity with the selectable digital gain. A control circuit may be configured to modify the digital and analog gains in response to an indication to switch between gain modes of the signal path, determine a noise floor of an audio signal comprising the digital input signal or a signal derived therefrom, and control modification of the digital and analog gains based on the noise floor.

At least some embodiments are directed to a system comprising an amplifier containing a first bias current source and configured to provide an output voltage at a node, a gain stage coupled to the node and comprising a second bias current source, and a buffer stage coupled to the node and comprising third and fourth bias current sources and an additional set of bias current sources, the third and fourth bias current sources are able to activate output transistors that are configured to increase current provided to a load. The system also comprises a controller configured to activate the first bias current source, to activate the second bias current source after the first bias current source is activated, to activate the bias current sources in the set after the first bias current source is activated, and to activate the third and fourth bias current sources after the first and second bias current sources are activated and after the bias current sources in the set are activated.

An analog signal path portion of a signal path may have: (i) an audio input for receiving an analog signal, an audio output for providing an output signal, and a selectable analog gain, and may be configured to generate the output signal based on the analog signal and in conformity with the selectable analog gain; and (ii) a digital path portion having a selectable digital gain and configured to receive a digital input signal and convert the digital input signal into the analog signal in conformity with the selectable digital gain. A control circuit may be configured to modify the digital and analog gains in response to an indication to switch between gain modes of the signal path, determine a noise floor of an audio signal comprising the digital input signal or a signal derived therefrom, and control modification of the digital and analog gains based on the noise floor.

At least some embodiments are directed to a system comprising an amplifier containing a first bias current source and configured to provide an output voltage at a node, a gain stage coupled to the node and comprising a second bias current source, and a buffer stage coupled to the node and comprising third and fourth bias current sources and an additional set of bias current sources, the third and fourth bias current sources are able to activate output transistors that are configured to increase current provided to a load. The system also comprises a controller configured to activate the first bias current source, to activate the second bias current source after the first bias current source is activated, to activate the bias current sources in the set after the first bias current source is activated, and to activate the third and fourth bias current sources after the first and second bias current sources are activated and after the bias current sources in the set are activated.

Semiconductor devices and methods are described wherein temperature dependence of leakage current in at least one pathway of a device is compensated by a resistor in the device. Control of temperature dependent leakage current is particularly useful for silicon nitride devices and for circuits such as cascode circuits. A semiconductor leakage current that increases with temperature may be compensated by a fabricated resistor such as a boron doped polysilicon resistor that is electrically connected to compensate the leakage current in the pathway.

Speed enhancement of data reading is achieved while suppressing an influence of an offset voltage of a differential amplifier. The differential amplifier includes: a current source that is connected to a first power supply in which a suppliable current is a first current; an active element pair that is connected to the current source, and amplifies a signal input to an input terminal pair to output an output signal pair; a load element pair that is connected to a second power supply different in power supply voltage from the first power supply, the load element pair serving for outputting the output signal pair to an output terminal pair; and a capacitance element pair that is inserted between an external input terminal pair and the input terminal pair; a switching element pair that charges the capacitance element pair to generate a voltage, which is obtained by converting an offset voltage of the input terminal pair into an input voltage, in the capacitance element pair by short-circuiting corresponding terminals between the output terminal pair and the input terminal pair; and a current control circuit that controls a current suppliable by the current source to a second current larger than the first current at a time of performing the charge.

A Gated CDS Integrator (GCI) may amplify low-level signals without introducing excessive offset and noise. The GCI may also amplify the low level signals with accurate and variable gain. The GCI may include a modulator preceding an amplifier such that offset or noise present in a signal path between the modulator and a demodulator input is translated to a higher out of band frequency, and thereafter reduced by a double sampled discrete time integrator which also reduces thermal noise. The thermal noise may also be reduced by averaging the output of the discrete time integrator.