An oscillating circuit has an injection-locked oscillator (ILO) and a calibration circuit. The ILO has a Gm cell and an LC tank. A first node of the Gm cell receives a first injection signal, and a second node of the Gm cell receives a second injection signal. The first injection signal and the second injection signal are differential signals. The Gm cell provides a negative resistance between a first output end and a second output end of the Gm cell. When the calibration circuit tunes a resonant frequency of the LC tank of the ILO, the magnitude of the negative resistance is reduced to control the ILO to stop self-oscillating. After finishing tuning the resonant frequency of the LC tank, the calibration circuit controls the ILO to start self-oscillating by increasing the magnitude of the negative resistance.

An amplifier includes an input stage, a folded cascode stage, and a class AB output stage. The folded cascode stage is coupled to the input stage. The class AB output stage is coupled to the folded cascode stage. The class AB output stage includes a high-side output transistor, a low-side output transistor, and a high-side feedback circuit that is coupled to the high-side output transistor. The high-side feedback circuit includes a high-side sense transistor and a high-side feedback transistor. The high-side sense transistor includes a control terminal that is coupled to a control terminal of the high-side output transistor. The high-side feedback transistor is coupled to an output of the high-side sense transistor and to the folded cascode stage. A first output of the folded cascode stage is coupled to the control terminal of the high-side sense transistor and to the control terminal of the high-side output transistor.

The present application discloses an amplification circuit. The amplification circuit includes an amplifier, a feedback unit, a second feedback unit, a first correlated double sampling unit, and a second correlated double sampling unit. The amplifier has a first positive input terminal, a second positive input terminal, a first negative input terminal, a second negative input terminal, a positive output terminal, and a negative output terminal. First terminals of the first feedback unit and the second feedback unit are coupled to the positive output terminal. The first correlated double sampling unit is coupled to the first negative input terminal and a second terminal of the first feedback unit, and performs a sample operation and an output operation. The second correlated double sampling unit is coupled to the second negative input terminal and a second terminal of the second feedback unit, and performs the sample operation and the output operation.

A compensated amplifier for use in a power converter controller. The compensated amplifier comprises a first amplifier, a second amplifier, an integrator, and an arithmetic operator. The first amplifier coupled to receive a sensed signal and a reference signal and configured to generate a first error signal in response to the sensed signal and the reference signal. The second amplifier coupled to the first amplifier and configured to generate a second error signal in response to the sensed signal and the reference signal. The integrator coupled to the first amplifier and configured to generate an integrated error signal in response to the first error signal. The arithmetic operator coupled to the integrator and to the second amplifier, wherein the arithmetic operator is configured to generate a control signal in response to the integrated error signal and the second error signal.

This applications relates to methods and apparatus for amplifying signals from capacitive transducers, in particular MEMS transducers such as MEMS capacitive microphones. An amplifier circuit has a signal node for receiving the input signal, a transducer biasing node for outputting a transducer bias voltage for biasing the capacitive transducer, and a voltage buffer configured to generate a buffered bias voltage at a buffer node. An amplifier arrangement is configured to receive the input signal from the signal node and the buffered bias voltage. The amplifier circuit comprises a signal path for supplying the buffered bias voltage to the transducer biasing node via a first capacitance, and the amplifier arrangement comprises a feedback resistor network configured such that: a change in input signal with respect to the buffered bias voltage results in a change in the output signal with respect to the buffered bias voltage with a gain greater than one; and a change in the buffered bias voltage results in a change in the output signal with a gain equal to one.

A method for enhancing linearity of the receiver front-end system includes receiving a radio frequency signal by an antenna, converting the radio frequency signal to first differential signals by a transformer module, adjusting frequencies of the first differential signals to generate second differential signals by a mixer module, detecting a common signal in order to reduce a common error of the second differential signals, and generating third differential signals according to a reference signal after the common error is reduced from the second differential signals. The first differential signals, the second differential signals, and the third differential signals are unbalanced.

An amplifier may include a main signal path having a plurality of stages compensated by feedback elements, the plurality of stages comprising an output stage configured to receive electrical energy from a power supply and an auxiliary path independent of the main signal path and comprising an output stage compensation circuit configured to generate a compensation current proportional to noise present in the power supply and apply the compensation current to cancel a power supply-induced current present in at least one of the feedback elements.

An amplifier includes an input stage, a folded cascode stage, and a class AB output stage. The folded cascode stage is coupled to the input stage. The class AB output stage is coupled to the folded cascode stage. The class AB output stage includes a high-side output transistor, a low-side output transistor, and a high-side feedback circuit that is coupled to the high-side output transistor. The high-side feedback circuit includes a high-side sense transistor and a high-side feedback transistor. The high-side sense transistor includes a control terminal that is coupled to a control terminal of the high-side output transistor. The high-side feedback transistor is coupled to an output of the high-side sense transistor and to the folded cascode stage. A first output of the folded cascode stage is coupled to the control terminal of the high-side sense transistor and to the control terminal of the high-side output transistor.

An amplifier circuit has a transducer biasing node for outputting a transducer bias voltage for biasing the capacitive transducer and a signal node for receiving the input signal. An amplifier arrangement comprising a feedback resistor network provides an amplified output signal. A voltage buffer provides a buffered bias voltage at a buffer node which is connected to a terminal of the feedback resistor network, to at least partly define the quiescent level of the output signal. The buffer node is electrically coupled to the transducer biasing node via a capacitance which may form part of a bias filter.

A communication circuit may include a first pair of digital-to-analog converters (DACs) coupled to an input of a first mixer and configured to generate first baseband signals. The communication circuit may further include a second pair of DACs coupled to an input of a second mixer and configured to generate second baseband signals. The second baseband signals may be shifted in phase relative to the first baseband signals.