A sample and hold circuit providing rail-to rail equivalent output is described. The circuit includes a sample and hold amplifier containing two separate sets of sampling capacitors, one set is coupled to a PMOS transistor differential stage and the other set is coupled to an NMOS transistor differential stage. The differential stages drive a current mirror based push-pull output differential stage to provide an output signal with ranges equivalent to a rail-to rail output signal swing.

An amplifier circuit includes a converter configured to convert a predefined physical quantity to a resistance value, and the resistance value converted by the converter is converted to a voltage value and then amplified. The converter includes variable resistance sensors of piezoresistance elements. A bias unit is configured to determine a bias current of the converter, and includes bias resistances. An operation amplifier unit receives, as input signals, output signals from the bias unit and the converter, and includes feedback resistances respectively connected to input and output ends of a first operational amplifier. The first operational amplifier is a whole differential operational amplifier including a common-mode feedback circuit.

At least some embodiments are directed to a system that comprises a differential input transistor pair (DITP) comprising first and second transistors, a first feedback loop coupled to the first transistor, and a second feedback loop coupled to the second transistor. When a differential voltage applied to the input stage is within a first range, the first and second feedback loops control a tail current supplied to the DITP, where the tail current at least partially determines a transconductance of the DITP. When the differential voltage is within a second range, the transconductance of the DITP is at least partially determined by a first resistor in the first feedback loop or by a second resistor in the second feedback loop.

A system is disclosed which allows for canceling high frequency rail to rail common mode swing at pulse-width modulation (PWM) frequency for a Class-D, H and G audio amplifier or a Linear Resonance Actuator (LRA) driver. This allows wide bandwidth current sensing without the need of external components, or large on-chip resistor-capacitor (RC) networks, facilitating integration of the sense resistor. In addition, the sense amplifier DC input common mode and audio band common mode swing is reduced, allowing a sense resistor high frequency common mode swing of a least twice the MOSFET gate break down voltages.

A switching amplifier includes a first half-bridge PWM modulator, a second half-bridge PWM modulator, and at least one amplifier stage configured to receive input signals. The switching amplifier also includes a PWM control stage configured to control switching of the first PWM modulator and of the second PWM modulator as a function of the input signals, by respective first PWM control signals and second PWM control signals. The amplifier stage and the PWM control stage have a fully differential structure.

A sample and hold circuit providing rail-to rail equivalent output is described. The circuit includes a sample and hold amplifier containing two separate sets of sampling capacitors, one set is coupled to a PMOS transistor differential stage and the other set is coupled to an NMOS transistor differential stage. The differential stages drive a current mirror based push-pull output differential stage to provide an output signal with ranges equivalent to a rail-to rail output signal swing.

A fully differential class-D amplifier having a controlled common-mode output voltage is disclosed. The differential class-D amplifier may include a correction circuit to determine the common-mode output voltage associated with differential pulse width modulated output signals and to generate differential correction signals to control the common-mode output voltage. In some exemplary embodiments, the differential class-D amplifier may include a plurality of gain stages to generate the differential PWM output signals. The differential correction signals may be provided to at least one stage of the differential class-D amplifier.

A switching amplifier includes a first half-bridge PWM modulator, a second half-bridge PWM modulator, and at least one amplifier stage configured to receive input signals. The switching amplifier also includes a PWM control stage configured to control switching of the first PWM modulator and of the second PWM modulator as a function of the input signals, by respective first PWM control signals and second PWM control signals. The amplifier stage and the PWM control stage have a fully differential structure.

A switching amplifier includes a first half-bridge PWM modulator, a second half-bridge PWM modulator, and at least one amplifier stage configured to receive input signals. The switching amplifier also includes a PWM control stage configured to control switching of the first PWM modulator and of the second PWM modulator as a function of the input signals, by respective first PWM control signals and second PWM control signals. The amplifier stage and the PWM control stage have a fully differential structure.

A fully differential class-D amplifier having a controlled common-mode output voltage is disclosed. The differential class-D amplifier may include a correction circuit to determine the common-mode output voltage associated with differential pulse width modulated output signals and to generate differential correction signals to control the common-mode output voltage. In some exemplary embodiments, the differential class-D amplifier may include a plurality of gain stages to generate the differential PWM output signals. The differential correction signals may be provided to at least one stage of the differential class-D amplifier.