An electronic circuit comprises a primary amplifier circuit including a differential input and an output, an offset nulling amplifier circuit, and an impedance matching circuit. The offset nulling amplifier circuit includes a differential input and an output. The differential input of the primary amplifier circuit is operatively coupled to a differential input of the offset nulling amplifier circuit and the impedance matching circuit. The output of the offset nulling amplifier circuit is operatively coupled to the primary amplifier circuit and provides a voltage to reduce offset in an output signal of the primary amplifier circuit.

A control apparatus for driving a display panel and a method thereof are provided. The control apparatus includes an image flickering detector and a chopper selector. The image flickering detector detects whether a present image pattern displayed on the display panel is flickering or not. The chopper selector selects a first chopper mode from a plurality of chopper modes for adjusting gamma voltages of a display image data, and detects whether the present image displayed on the display panel according to the display image data is flickering or not by the image flickering detector. The chopper selector selects a second chopper mode to adjust the gamma voltages of the display image data in response to the present image being flickering. The first chopper mode is different from the second chopper mode.

A current sensor integrated circuit to sense a current through a resistor includes a substrate, a tub disposed in the substrate, an analog front end disposed in the tub and comprising an amplifier having inputs coupled across the resistor and a charging circuit configured to bias the analog front end and the tub to a bias voltage that is a predetermined offset voltage greater than a common mode voltage associated with the resistor. In embodiments, the analog front end is biased to a first bias voltage and the tub is biased to a second, different bias voltage.

Apparatus for performing offset cancellation is disclosed. The apparatus comprises a gating circuit (6) for receiving an analogue signal (3) from a source (2) and providing a gated analogue signal (9) to an analogue circuit (10), a gating controller (7; 14; FIG. 1) and a digital processor (14; FIG. 1) for receiving a digital signal (13) converted from an analogue output (11) from the analogue circuit (10). The gating circuit comprises at least one path (21.sub.1), each path respectively comprising, an input terminal (22.sub.1), an output terminal (23.sub.1), a node (24.sub.1) interposed between the input and output terminals, a first transistor (Q1) having a channel arranged between the input terminal and the node, and a second transistor (Q3) having channel arranged between the node and a fixed reference, such as ground (GND). The gating controller is configured, in a first time window (15.sub.A), to switch the first transistor so that the input terminal and the output terminal are decoupled and to switch the second transistor so that the node is coupled to the fixed reference. The gating controller is configured, in a second, different time window (15.sub.B), to switch the second transistor so that the node and the fixed reference are decoupled and to switch the first transistor so that the input terminal is coupled to the input terminal. The digital processor is configured, in the first time window, to take a first measurement of the digital signal, and, in the second, different time window, to take a second measurement of the digital signal. The digital processor configured to subtract the first measurement from the second measurement.

Systems, apparatuses, and methods for performing offset correction for pseudo differential signaling are disclosed. An apparatus includes at least a sense amplifier and an offset correction circuit. The offset correction circuit generates an offset correction voltage by applying a positive or negative offset to a termination voltage. The offset correction circuit supplies the offset correction voltage to a negative input terminal of the sense amplifier. An input signal voltage is supplied to the positive input terminal of the sense amplifier. The sense amplifier generates an output based on a comparison of the voltages supplied to the positive and negative input terminals.

A system for a differential trans-impedance amplifier circuit comprising: an amplifier having a pair of input nodes and configured to generate an amplified replica of a differential voltage on said pair of input nodes; a photodiode; a pair of capacitors coupling said photodiode to said pair of input nodes; at least one resistance coupled between said pair of input nodes of said amplifier; and a bias network comprising two photodiode biasing resistances each photodiode biasing resistance coupled in series between said photodiode and a respective DC voltage. A feedback loop for the amplifier may include source followers that are operable to level shift voltages prior to coupling capacitors that couple said photodiode to said amplifier to ensure stable bias conditions for said amplifier. The source followers may include CMOS transistors. The amplifier may be integrated in a complementary metal-oxide semiconductor (CMOS) chip, which may include a CMOS photonics chip.

A read-out circuitry for acquiring a multi-channel biopotential signal, comprises: a plurality of read-out signal channels, each receiving an input signal from a unique signal electrode; a reference channel receiving a reference signal from a reference electrode; wherein each read-out signal channel and the reference channel comprises a channel amplifier connected to receive the input signal in a first input node and with an output node connected to a second input node via a channel feedback loop; wherein each signal channel amplifier comprises a capacitor between the second input nodes of the signal channel amplifier and the reference channel amplifier, and wherein each signal channel feedback loop and the reference channel feedback loop comprise a filter.

The present disclosure includes a photodetector element (11) that converts an optical signal into an electric current signal; a transimpedance amplifier (12a) that converts the electric current signal into a voltage signal; a differential amplifier (12d) that converts the voltage signal into a differential signal, by performing differential amplification of a difference between the voltage signal and a threshold voltage; an LOS detection circuit that detects a no-signal section of the optical signal; and an MCU that repeatedly executes offset cancellation processing, the offset cancellation processing including threshold voltage change processing in which the threshold voltage is changed such that an offset voltage of the differential signal is reduced, the MCU 13 skipping the threshold voltage change processing in the no-signal section.

A chopper amplifier circuit includes a first amplifier path, a second amplifier path, and a third amplifier path. The first amplifier path includes chopper circuitry configured to modulate an input signal and an offset voltage at a chopping frequency, and ripple reduction circuitry configured to attenuate the chopping frequency in a signal in the first amplifier path. The second amplifier path includes a feedforward gain stage, and is configured to apply higher gain to intermediate signal frequencies than is applied in the first amplifier path. The third amplifier path includes a feedforward gain stage, and is configured to apply higher gain to high signal frequencies than is applied in the first amplifier path and the second amplifier path. The intermediate signal frequencies are lower than the high signal frequencies.

A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.