A power conversion apparatus can include: a power module configured to transfer an analog sensing signal corresponding to a current of an inductor and a voltage applied at both terminals of a capacitor, and to perform power conversion by driving a power semiconductor with a pulse-width modulation signal; and a controller configured to receive the analog sensing signal from the power module, to convert the analog sensing signal to a digital signal, to generate the pulse-width modulation signal, and to transfer the pulse-width modulation signal to the power module.

In a cascaded integrator comb (CIC) filter, a time-varying gain is added before the last integrating stage transforming its sub optimal boxcar impulse response into an FIR filter of arbitrary length. Make the coefficients sparse and taking them from a set of small integers leads to an efficient hardware implementation that does not compromise any of the essential CIC filter characteristics especially the overflow handling. The proposed sparse CIC structure can improve the worst case stop band attenuation by as much as 10 dB while occupying 77% of the chip area and consuming 30% less power compared to a standard a 5.sup.th order CIC filter, and reducing the overall bit growth of the filter and the amount of high rate operations. Design examples are given illustrating the advantages and flexibility of the proposed structure.

A digital filtering method includes receiving a digital signal, and passing the digital signal through a Pth order comb cascade. The method includes beginning pre-computing of intermediate integrator states of a Pth order integrator cascade as a function of the digital signal, prior to receiving output from a last comb of the Pth order comb cascade. The outputs from each comb of the Pth order comb cascade are then applied to the pre-computed intermediate integrator states to thereby produce a filtered version of the digital signal. The Pth order comb cascade may operate at a sampling frequency, and the pre-computing of the intermediate integrator states is performed at the sampling frequency, while the application of the outputs from each comb of the Pth order comb cascade to the pre-computed intermediate integrator states is performed at a multiple of the sampling frequency.

Filters are discussed where a first window function and a second window function are applied to a digital input signal, wherein a window length of the first window function is longer than a window length of the second window function. The results of this windowing are integrated.

A digital filter includes: integration calculation units (10) that are cascade-connected, are fed time-division-multiplexed data, the time-division-multiplexed data being formed of pieces of data on M channels that are time-division multiplexed, the pieces of data on the respective channels being updated at a rate equal to a sampling frequency f.sub.s, operate in accordance with a clock having a frequency f.sub.sM, and integrate the time-division-multiplexed data for every M samples; a frequency conversion unit (11) that operates in accordance with a clock having a frequency f.sub.DM, decimates data at the sampling frequency f.sub.s input from the integration calculation unit (10) in the last stage at a sampling frequency f.sub.D, and delays data obtained as a result of decimation by (M1) samples; and difference calculation units (12) that operate in accordance with the clock having the frequency f.sub.DM, are cascade-connected to the output of the frequency conversion unit (11), and each subtract, from data input thereto, data M samples before.

Techniques to increase a data throughput rate of a filter circuit by preloading selectable memory circuits of the filter circuit with reference data, sampling input data at an input of the filter circuit, combining the sampled input data with the preloaded reference data, and generating a filter output based on the combined sampled input data and preloaded reference data.

A digital up-converter (DUC) includes a cascaded combinator-differentiator (CCD) filter, a low-pass filter, an up-sampler, and a down-sampler. The combinator includes a number of series-connected combinator stages and the differentiator includes a number of series-connected differentiator stages. The CCD filter functions similarly to an interpolator filter, filtering and up-sampling the baseband signal out of the baseband. In one embodiment, the up-sampling factor is twice the number of channels (2N). The disclosed DUC does not require complex mixers or oscillators. Also, the low-pass filter of the DUC does not require a narrow transition band, so the number of coefficients for the low-pass filter is relatively low.

A digital up-converter (DUC) includes a cascaded combinator-differentiator (CCD) filter, a low-pass filter, an up-sampler, and a down-sampler. The combinator includes a number of series-connected combinator stages and the differentiator includes a number of series-connected differentiator stages. The CCD filter functions similarly to an interpolator filter, filtering and up-sampling the baseband signal out of the baseband. In one embodiment, the up-sampling factor is twice the number of channels (2N). The disclosed DUC does not require complex mixers or oscillators. Also, the low-pass filter of the DUC does not require a narrow transition band, so the number of coefficients for the low-pass filter is relatively low.

An improved sliding discrete Fourier transform (SDFT) algorithm called CIC-SDFT and its apparatus are provided. An input signal is multiplied by a modulated twiddle factor, and is then processed by a modified cascade integrator-comb (CIC) filter. The CIC-SDFT comprises an integrator section and a comb section, with a downsampler disposed between the two sections to enable downsampling of the SDFT computations. Through addition of more integrator stages and comb stages to the CIC-SDFT, the accuracy of spectrum estimation may be improved in a computationally inexpensive manner and with less complexity than applying windowing functions to known SDFTs. Various embodiments provide a partially-nonrecursive method of CIC-SDFT that further decreases computational complexity.

A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.