Various exemplary embodiments are directed to methods including obtaining an input sample magnitude, filtering the obtained input sample magnitude, generating a sample-to-sample difference based on the filtered input sample magnitude, and engaging an actuator in accordance with a determination that the sample-to-sample difference satisfies a rate threshold. In addition, various exemplary embodiments are directed to devices including a processor, a control sensor operatively coupled to the processor and operable to obtain an input sample magnitude, an input filter operatively coupled to the processor and operable to filter the at least one obtained input magnitude sample, a non-transitory computer-readable medium operatively coupled to the processor and including a rate engine operable to generate a sample-to-sample difference based on the filtered input sample magnitude, and to generate a determination that the sample-to-sample difference satisfies a rate threshold, and a control actuator operatively coupled to the processor and operable to engage an operation mechanism in accordance with the determination that the sample-to-sample difference satisfies a rate threshold.

A digital signal processor is designed to channelize an input signal, and includes a channelizer circuit and a plurality of tuning modules. The channelizer circuit is designed to receive an input signal having a first bandwidth and to channelize the input signal into a first set of channels each having a bandwidth smaller than the first bandwidth as a first output signal and to channelize the input signal into a second set of channels having a bandwidth smaller than the first bandwidth as a second output signal. The plurality of tuning modules are designed to receive one or more channels from the first output signal or the second output signal and to further downsample the one or more channels to a user-defined bandwidth at a user-defined center frequency. Each of the plurality of tuning modules include a plurality of FIR filter blocks and a memory having a plurality of FIR filter coefficients.

Systems and method for resampling are provided. A method of resampling includes receiving a first sampled signal that is sampled at a first sample rate, where the first sample rate is a submultiple of a system clock rate for a Farrow filter. The method further includes resampling the first sampled signal, using the Farrow filter having a plurality of finite impulse response (FIR) filters and an arbitrary position interpolator, at a second sample rate to generate a second sampled signal. The interpolation factor for each sample of the second sampled signal is retrieved from at least one lookup table stored in memory and the first sample rate and the second sample rate are fixed and locked to a common frequency reference. The method further includes outputting the second sampled signal at the second sample rate.

The present disclosure provides a resampling apparatus and a resampling method. The resampling apparatus includes a control unit, a memory device, a resolution identifier, a phase rate generator, a coefficient generator, and a resample filter. The control unit controls reading and writing operations of the resampling apparatus according to a control signal. The memory device transmits the control signal to the control unit. The resolution identifier sets a resolution bandwidth identity according to an interpolation/decimation (I/D) value of the control signal. The phase rate generator generates a phase select signal and a counter enable signal according to the resolution bandwidth identity. The coefficient generator generates a coefficient select signal according to the resolution bandwidth identity. The resample filter generates a resampled output data according to the phase select signal, the coefficient select signal, and an input data.

Aspect of the present disclosure provide for a circuit. In an example, the circuit comprises a multiplexer having a first input, a second input, a control input, and an output. The circuit further comprises a first register having an input coupled to the output of the multiplexer and an output. The circuit further comprises a second register having an input coupled to the output of the first register and an output. The circuit further comprises a subtractor having a first input coupled to the output of the multiplexer and a second input coupled to the output of the second register. The circuit further comprises a third register having an input coupled to the output of the subtractor and an output coupled to the first input of the multiplexer.

A process for processing a digital signal comprises constructing a fractional order control system that models a desired frequency response by assembling filter components from a filter component library. The filter components are defined by Laplace functions that include a non-integer control order having a variable fractional scaling exponent. Then, the fractional order control system is adjusted by applying an altitude exponent to the fractional order control system, and the altitude exponent changes a magnitude of the frequency response without changing a width of a transition band of the frequency response. An input signal in the digital frequency domain is received and processed based upon the fractional order control system to generate a digital output that is conveyed.

One example includes a digital signal conditioner (DSC) system. A sample selector bank receives a digital sample block of an input signal that is provided at a supported input oversampling factor and selects a subset of samples from the digital sample block based on a selection signal. A tap weights selector bank generates a set of tap weights based on the selection signal. A filter bank receives the subset of the samples from each of the sample selectors and a respective set of tap weights. Each filter provides a weighted sample associated with the respective subset of samples and the respective set of tap weights. A reformattor receives the weighted sample from each of the filters and provides a filtered sample block including the weighted sample from a subset of the filters at an output oversampling factor for each supported input oversampling factor based on a selected supported resampling ratio.

A sample rate converter (SRC) for implementing a rate conversion L/M is described wherein data is input to the SRC at an input rate (F.sub.in) and output from the SRC at an output rate (F.sub.out) equal to F.sub.in*L/M. The SRC includes a low pass filter (LPF) including P multiply-add instances, wherein P is a parallelization factor of the SRC; an input formatter for arranging samples received at the SRC in accordance with the rate conversion L/M and providing P*T.sub.pp input samples to the filter at a given time, wherein T.sub.pp is a number of taps per phase of the LPF; and a coefficient bank for storing a plurality of coefficients and for providing P*T.sub.pp of the coefficients to the LPF at a given time.

Accelerometers are described herein that have RMS outputs. For instance, an example accelerometer may include a MEMS device and an ASIC. The MEMS device includes a structure having an attribute that changes in response to acceleration of an object. The ASIC determines acceleration of the object based at least in part on changes in the attribute. The ASIC includes analog circuitry, an ADC, and firmware. The analog circuitry measures the changes in the attribute and generates analog signals that represent the changes. The ADC converts the analog signals to digital signals. The firmware includes RMS firmware. The RMS firmware performs an RMS calculation on a representation of the digital signals to provide an RMS value that represents an amount of the acceleration of the object.

Aspect of the present disclosure provide for a circuit. In an example, the circuit comprises a multiplexer having a first input, a second input, a control input, and an output. The circuit further comprises a first register having an input coupled to the output of the multiplexer and an output. The circuit further comprises a second register having an input coupled to the output of the first register and an output. The circuit further comprises a subtractor having a first input coupled to the output of the multiplexer and a second input coupled to the output of the second register. The circuit further comprises a third register having an input coupled to the output of the subtractor and an output coupled to the first input of the multiplexer.