Patent classifications
H03H17/0685
DATA PROCESSOR, DATA PROCESSING METHOD AND COMMUNICATION DEVICE
A parallel transfer rate converter inputs first parallel data with number of samples being S1 pieces in synchronism with a first clock, and outputs second parallel data with number of samples being S2=S1(m/p) pieces (p is an integer equal to or larger than 1) in synchronism with a second clock having a frequency which is p/m times of a frequency of the first clock. A convolution operation device inputs the second parallel data in synchronism with the second clock, generates third parallel data with number of samples being S3=S2(n/m) pieces (S3 is an integer equal to or larger than 1) by executing a convolution operation with a coefficient indicating a transmission characteristic to the second parallel data, and outputs the third parallel data in synchronism with the second clock.
AUDIO RECORDING DEVICE, AUDIO RECORDING SYSTEM, AND AUDIO RECORDING METHOD
Deterioration in audio quality is inhibited in a device which records audio and stretches a reproduction time period. A sampling processing unit performs processing of sampling audio in a predetermined period at a sampling rate higher than a predetermined sampling rate to generate audio data as high-resolution audio data, and processing of sampling audio outside the predetermined period at the predetermined sampling rate to generate audio data as normal audio data. Also, a reproduction time conversion unit stretches the reproduction time period of the high-resolution audio data.
Analog-digital compatible re-sampling
A re-sampler comprises: a plurality of multipliers configured to receive an input sample; and a plurality of accumulators coupled to the multipliers and configured to form multiplier-accumulator (MAC) units with the multipliers, wherein the MAC units are configured to: compute partial products from the input sample, accumulate the partial products over clock cycles, and sequentially generate output samples based on the computing and the accumulating. A method comprises: receiving input samples; computing partial products from the input samples; accumulating the partial products over clock cycles; and sequentially generating output samples based on the computing and the accumulating.
METHOD AND DEVICE FOR EMULATING CONTINUOUSLY VARYING FRAME RATES
The present invention relates to a method and a device for emulating frame rates in video or motion picture.
MIX BUFFERS AND COMMAND QUEUES FOR AUDIO BLOCKS
The subject disclosure is directed towards a technology that may be used in an audio processing environment. Nodes of an audio flow graph are associated with virtual mix buffers. As the flow graph is processed, commands and virtual mix buffer data are provided to audio fixed-function processing blocks. Each virtual mix buffer is mapped to a physical mix buffer, and the associated command is executed with respect to the physical mix buffer. One physical mix buffer mix buffer may be used as an input data buffer for the audio fixed-function processing block, and another physical mix buffer as an output data buffer, for example.
Mix buffers and command queues for audio blocks
The subject disclosure is directed towards a technology that may be used in an audio processing environment. Nodes of an audio flow graph are associated with virtual mix buffers. As the flow graph is processed, commands and virtual mix buffer data are provided to audio fixed-function processing blocks. Each virtual mix buffer is mapped to a physical mix buffer, and the associated command is executed with respect to the physical mix buffer. One physical mix buffer mix buffer may be used as an input data buffer for the audio fixed-function processing block, and another physical mix buffer as an output data buffer, for example.
Cascaded integrator-comb filter as a non-integer sample rate converter
The implementation of non-integer sample rate conversion and filtering of data sequences may be improved by performing both operations together with a system that includes a CIC filter and a control block that modifies internal states of the CIC filter. In one embodiment, input data samples provided at a first sample rate may be filtered by a CIC filter that includes a cascade of an integrating stage and a comb filter stage, each stage operating at a different sampling rate. A control block coupled to the CIC filter may modify at least one internal state of at least one of the integrating stage and comb filter stage of the CIC filter, wherein filtering by the CIC filter and modifying the at least one internal state causes the CIC filter to output data samples at a second sample rate unequal to the first sample rate.
ANALOG-DIGITAL COMPATIBLE RE-SAMPLING
A re-sampler comprises: a plurality of multipliers configured to receive an input sample; and a plurality of accumulators coupled to the multipliers and configured to form multiplier-accumulator (MAC) units with the multipliers, wherein the MAC units are configured to: compute partial products from the input sample, accumulate the partial products over clock cycles, and sequentially generate output samples based on the computing and the accumulating. A method comprises: receiving input samples; computing partial products from the input samples; accumulating the partial products over clock cycles; and sequentially generating output samples based on the computing and the accumulating.
LOW-LATENCY DATA ACQUISITION USING SIGMA-DELTA MODULATORS
In examples, a device includes a cascade of integrators (COI) filter including an accumulator having an output and a decimator having an input coupled to the output of the accumulator. An output of the decimator is an output of the COI filter. The device includes a SINC filter including the accumulator and the decimator of the COI filter. The SINC filter further includes a differentiator having an input coupled to the output of the decimator, in which an output of the differentiator is an output of the SINC filter. The device also includes a multiplexer having an output and first and second inputs. The first input of the multiplexer is coupled to the output of the COI filter, and the second input of the multiplexer is coupled to the output of the SINC filter.