The present disclosure relates to a phase-locked loop (PLL) including a frequency detector, a sub-sampling phase detector (SSPD), and a voltage-controlled oscillator (VCO). The frequency detector is configured to receive a reference signal and an output signal, and to generate a coarse-tuning voltage that indicates a frequency difference between the reference signal and the output signal. The SSPD is configured to sub-sample the output signal using the reference signal, and to generate a fine-tuning voltage that indicates a phase difference between the reference signal and the output signal. The VCO is configured to update the output signal based on the coarse-tuning voltage and the fine-tuning voltage.

An injection locked oscillator (ILO) circuit is disclosed. The ILO circuit may include a first clock injection stage including a first programmable inverter in series with a first self-biased inverter. The first injection stage may receive a first input clock having a first frequency and generate a first injection signal. The ILO circuit may further include a second clock injection stage including a second programmable inverter in series with a second self-biased inverter. The second injection stage may receive a second input clock signal having the first frequency and to generate a second injection signal. The ILO may further include a phase locked loop (PLL) stage including a multi-stage ring oscillator. The PLL stage may receive the first injection signal and the second injection signal and to generate an output clock signal based at least in part on the first frequency.

A memory includes: a clock generation circuit, configured to generate a first oscillation signal and a second oscillation signal. The first oscillation signal and the second oscillation signal have a same frequency but opposite phases, and a duty cycle of the first oscillation signal and a duty cycle of the second oscillation signal are both within a first preset range. The memory further includes a differential input circuit, which is configured to receive a first external signal and a second external signal, and generate a first internal signal and a second internal signal. The clock generation circuit is configured to monitor the duty cycle of the first internal signal or the duty cycle of the second internal signal, and enable the duty cycle of the first internal signal or the duty cycle of the second internal signal to be within a second preset range.

Various embodiments described herein provide a multiple injection lock ring-based PI that can inject a plurality of clock signals, of different phases, at injection points disposed along the ring chain of the PI and lock phase to those received clock signals (injected clock signals). For instance, an embodiment described herein may provide a multiple injection lock ring-based PI that permits double injection, triple injection, or the like, of clock signals external into the PI.

Aspects of the disclosure are directed to quadrature clock generation with injection locking. In accordance with one aspect, quadrature clock generation with injection locking uses a digital calibration circuit having a coarse calibration circuit and a fine calibration circuit to perform a coarse frequency calibration of a controlled oscillator, wherein the controlled oscillator is coupled to the digital calibration circuit; characterize a replica oscillator signal path associated with an oscillator replica circuit, wherein the oscillator replica circuit is coupled to the controlled oscillator; perform a fine frequency calibration of the controlled oscillator by measuring a phase difference between the controlled oscillator and the oscillator replica circuit; and generate a calibrated set of quadrature clock signals after performing the fine frequency calibration of the controlled oscillator.

A ring oscillator includes first to fourth current-controlled delay circuits configured to allow a delay time to be changed depending on a magnitude of sink current, wherein the first to fourth current-controlled delay circuits are arranged symmetrically to each other about a square.

An area efficient amplifier that amplifies a continuous-time continuous-amplitude signal and converts it to a discrete-time discrete-amplitude signal. The amplifier includes a first oscillator having an input and a plurality of N outputs and a second oscillator having an input and N outputs. The amplifier includes N phase detectors, each phase detector has a first input, a second input, a first output, and a second output, where each first input of each phase detector is coupled to respective one of the N outputs of the first oscillator, where each second input of each phase detector is coupled to respective one of the N outputs of the second oscillator. The amplifier includes N quantizers, each quantizer has a data input, a clock input, and an output, where each data input of each quantizer is coupled to respective one first output or one second output of the N phase detectors.

Aspects of the disclosure are directed to quadrature clock generation with injection locking. In accordance with one aspect, quadrature clock generation with injection locking uses a digital calibration circuit having a coarse calibration circuit and a fine calibration circuit to perform a coarse frequency calibration of a controlled oscillator, wherein the controlled oscillator is coupled to the digital calibration circuit; characterize a replica oscillator signal path associated with an oscillator replica circuit, wherein the oscillator replica circuit is coupled to the controlled oscillator; perform a fine frequency calibration of the controlled oscillator by measuring a phase difference between the controlled oscillator and the oscillator replica circuit; and generate a calibrated set of quadrature clock signals after performing the fine frequency calibration of the controlled oscillator.

A system for providing security in a computer system is provided. The system includes a ring oscillator including a plurality of logic gates connected in a ring configuration. The system also includes logic circuits to start the ring oscillator by a ring-enable signal and a clock signal provided to a clock input of at least one controlled logic gate of the plurality of logic gates. The clock signal controls the at least one controlled logic gate and thereby synchronizes the ring oscillator to the clock signal. The clock signal is provided to the clock input for a predetermined warm-up duration, and thereafter, the logic circuits restart and operate the ring oscillator without the clock signal.

A realignment ring-cell circuit is disclosed. The circuit includes a single-to-differential unit, an OR gate, an AND gate, a first P-type metal-oxide-semiconductor transistor, and a first N-type metal-oxide-semiconductor transistor. The single-to-differential unit has an input configured to receive a realignment signal, a first output for outputting a first differential output and a second output for outputting a second differential output. The first output for outputting is a first input to the OR gate. The second output for outputting is a first input to the AND gate. A gate of the P-type metal-oxide-semiconductor transistor is electrically connected to an output of the OR gate. A gate of the N-type metal-oxide-semiconductor transistor is electrically connected to an output of the AND gate. A drain of the P-type metal-oxide-semiconductor transistor and a drain of the N-type metal-oxide-semiconductor transistor are electrically connected to each other and are further electrically connected to a second input of the OR gate and a second input of the AND gate.