A realignment ring-cell circuit is disclosed. The circuit includes a single-to-differential unit, an OR gate, an AND gate, a first P-type metal-oxide-semiconductor transistor, and a first N-type metal-oxide-semiconductor transistor. The single-to-differential unit has an input configured to receive a realignment signal, a first output for outputting a first differential output and a second output for outputting a second differential output. The first output for outputting is a first input to the OR gate. The second output for outputting is a first input to the AND gate. A gate of the P-type metal-oxide-semiconductor transistor is electrically connected to an output of the OR gate. A gate of the N-type metal-oxide-semiconductor transistor is electrically connected to an output of the AND gate. A drain of the P-type metal-oxide-semiconductor transistor and a drain of the N-type metal-oxide-semiconductor transistor are electrically connected to each other and are further electrically connected to a second input of the OR gate and a second input of the AND gate.

The present application discloses an oscillation device and a method for oscillation thereof, in which a control signal is generated from a control circuit to a ring oscillation circuit. The ring oscillation circuit generates an oscillation signal with a first signal frequency at start up oscillation, firstly. Further, the ring oscillation circuit modulates an oscillation frequency to drive the oscillation signal change from the first signal frequency to a higher second signal frequency. Thus, the present application provides the ring oscillation device generating the oscillation signal with a lower frequency at starting up oscillation, and then make the oscillation signal change to a higher frequency. Hereby, the present application provides the oscillation signal operated at a higher operating frequency.

An injection-locked oscillator includes an oscillator and an injection circuit. The oscillator includes a first oscillation node through which a first oscillation signal is output and a second oscillation node through which a second oscillation signal is output, the second oscillation signal having a phase opposite to that of the first oscillation signal. The injection circuit provides an injection current between the first oscillation node and the second oscillation node according to a reference signal. The injection circuit includes a charging element configured to be charged or discharged in response to a reference signal and to provide the injection current between the first oscillation node and the second oscillation node.

A variable delay circuit includes first pull-up and first pull-down current paths and second pull-up and second pull-down current paths. The variable delay circuit generates first delays in an output signal relative to an input signal in response to the first pull-up and first pull-down current paths being enabled by a first control signal. The variable delay circuit generates second delays in the output signal relative to the input signal that are different than the first delays in response to the second pull-up and second pull-down current paths being enabled by a second control signal.

Embodiments of the present disclosure relate to various methods and example systems for carrying out analog-to-digital conversion of data acquired by arrays of nanogap sensors. The nanogap sensors described herein may operate as molecular sensors to help identify chemical species through electrical measurements using at least a pair of electrodes separated by a nanogap. In general, the methods and systems proposed herein rely on digitizing the signal as the signal is being integrated, and then integrating the digitized results. With such methods, the higher sample rate used in the digitizer reduces the charge per quantization and, therefore, the size of sampling capacitors used. Consequently, sampling capacitors may be made factors of magnitude smaller, requiring less valuable space on a chip compared to sampling capacitors used in conventional nanogap sensor arrays.

A signal may be arbitrarily delayed in discrete steps by an arbitrary delay buffer having an analog delay and a digital delay. An analog delay may have a number of selectable delay stages (e.g. ring oscillator with VCDL stages). A digital delay may have rising and falling edge detectors, resettable ring oscillators that oscillate in response to rising or falling edges and counters to count oscillations and generate rising and falling edge delay signals when oscillation counts reach rising and falling edge delay counts. A resettable ring oscillator may have a resettable stage (e.g. VCDL) that may be enabled and disabled. Selection of one or both digital and analog delays and respective delay times may be based on one or more characteristics. For example, an analog delay may delay an input signal or a delayed input signal received from the digital delay based on input signal frequency or total delay.

Systems and methods disclosed herein provide for effectively eliminating the rotational and static phase skews between the in-phase (I) and quadrature (Q) clocks generated by phase interpolators in decision feedback equalizer based receivers. Embodiments of the systems and methods provide for (i) a ring oscillator that eliminates the rotational phase skews and (ii) a plurality of clock mixers that eliminate the static phase skews.

A ring oscillator includes first to fourth current-controlled delay circuits configured to allow a delay time to be changed depending on a magnitude of sink current, wherein the first to fourth current-controlled delay circuits are arranged symmetrically to each other about a square.

A ring oscillator includes: (i) one or more current sources each connected to a supply voltage source; and (ii) oscillation elements connected in series in a ring configuration, each oscillation element including: (a) first and second input terminals; (b) first and second output terminals; (c) first and second inverters receiving input signals from the first and second input terminals, respectively, and providing output signals on the first and second output terminals, respectively; and (d) third and fourth inverters, each having an input terminal and an output terminal, wherein the input terminals of the third and fourth inverters are coupled to the first and second output terminals of the oscillator element, respectively, wherein the output terminals of third and fourth inverters are coupled to the second and first output terminals of the oscillator element, respectively, and wherein each of first, second, third and fourth inverters are coupled to the supply voltage source through the current sources.

Clock generation from an external reference by generating a reference clock gating signal using a reference clock gating circuit; enabling a ring-oscillator-injection mode using the reference clock gating signal to disable a first buffer of a ring oscillator and to enable a reference clock injection buffer, the first buffer and the injection buffer having parallel connected outputs that connect to a next buffer input; receiving a reference clock transition of a reference clock signal at the injection buffer and injecting it into the next buffer; and enabling a ring-oscillator-closed-loop mode by using the reference clock gating signal to enable the first buffer and to disable the reference clock injection buffer.