The invention relates to a multi-phase oscillator for generating multiple phase-shifted oscillator signals including: a ring oscillator having a number of concatenated oscillator delay cells which are interconnected to generate an oscillator signal, wherein phase-shifted oscillator signals are generated between the oscillator delay cells; a phase-blending unit configured to receive two phase-shifted oscillator signals and to generate a mid-phase oscillator signal whose phase shift is between the shifts of the two phase-shifted oscillator signals; and an interpolator delay line having a number of concatenated interpolator delay cells to generate further phase-shifted oscillator signals.

The present application discloses an oscillation device and a method for oscillation thereof, in which a control signal is generated from a control circuit to a ring oscillation circuit. The ring oscillation circuit generates an oscillation signal with a first signal frequency at start up oscillation, firstly. Further, the ring oscillation circuit modulates an oscillation frequency to drive the oscillation signal change from the first signal frequency to a higher second signal frequency. Thus, the present application provides the ring oscillation device generating the oscillation signal with a lower frequency at starting up oscillation, and then make the oscillation signal change to a higher frequency. Hereby, the present application provides the oscillation signal operated at a higher operating frequency.

Systems, devices, and methods are described herein for aligning a phase of a ring oscillator and removing jitter. An oscillator includes a resistor bank array, an operational amplifier, a first and second transistor, and a realignment circuit. The resistor bank array has a plurality of resistors configured to generate a first signal. The operational amplifier is coupled to a PLL circuit and is configured to compare a voltage of the PLL circuit with a voltage of the resistor bank array. The first transistor is coupled between the operational amplifier and a ring oscillator. The first transistor is configured to generate a second signal to control a frequency of the ring oscillator during a realignment state. The realignment circuit is coupled to the first transistor and the ring oscillator. The realignment circuit is configured to generate a realignment signal to align the ring oscillator with a first clock signal.

An injection-locked oscillator includes a plurality of delay elements, two or more voltage control circuits, a phase comparator and a controller. The plurality of delay elements is connected in a loop and coupled to a global power supply. Each delay element has an input driven by a preceding stage and an output that drives a next stage. Each voltage control circuit couples one of the plurality of delay elements to the global power supply. The phase comparator is coupled to in-phase and quadrature outputs of the injection-locked oscillator. The controller is coupled to an output of the phase comparator and is configured to drive control inputs of the two or more voltage control circuits. The control input of each voltage control circuit determines a level of a voltage drop across the each voltage control circuit.

An injection locked frequency divider is disclosed. The injection-locked frequency divider includes a sub-harmonic injection-locked oscillator, a reference clock divider, a counter, and a variable load resistor control unit. The sub-harmonic injection-locked oscillator has variable load resistors that are adjusted in response to a resistance adjustment signal, and, when oscillation frequency determined based on the magnitudes of the variable load resistors is a sub-harmonic of an injection signal, outputs signals having the oscillation frequency as divided output signals. The reference clock divider generates a count-enable signal from a reference clock signal according to a reference division ratio. The counter generates divided output count signals based on the divided output signals in response to the count-enable signal. The variable load resistor control unit compares target count values, determined based on the target frequencies of the divided output signals, with the divided output count signals, and outputs the resistance adjustment signal.

Various aspects of an injection-locked oscillator and method for controlling jitter and/or phase noise are disclosed herein. In accordance with an embodiment, an injection-locked oscillator includes one or more circuits that are configured to receive a pair of complementary phase output signals from one or more gain stages of the injection-locked oscillator. The one or more circuits may be configured to receive one or more switching signals. The received pair of complementary phase output signals are shorted by use of the one or more received switching signals. The shorting reduces the phase difference between an input signal and an output signal of the injection-locked oscillator.

Methods and apparatuses featuring a multiplying injection-locked oscillator are described. Some embodiments include a pulse-generator-and-injector and one or more injection-locked oscillators. The outputs of the pulse-generator-and-injector can be injected into corresponding injection points of an injection-locked oscillator. In embodiments that include multiple injection-locked oscillators, the outputs of each injection-locked oscillator can be injected into the corresponding injection points of the next injection-locked oscillator. Some embodiments reduce deterministic jitter by dynamically modifying the loop length of an injection-locked oscillator, and/or by using a duty cycle corrector, and/or by multiplexing/blending the outputs from multiple delay elements of an injection-locked oscillator.

The present disclosure provides a voltage-controlled oscillator for a phase-lock loop circuit. The voltage-controlled oscillator is used to receive a control voltage and generate a clock signal, and includes a voltage-to-current device, a process compensation device, a subtraction unit and a clock signal generating module. The voltage-to-current device is used to generate a linear current according to the control voltage. The process compensation device is used to generate a compensation current according to the control voltage. The compensation current is proportional to a transistor operation speed corresponding to a process offset. The subtraction unit is electrically connected to the voltage-to-current device and the process compensation device, and is used to subtract the compensation current from the linear current to generate the control current. The clock signal generating module is electrically connected to the subtraction unit, and is used to generate the clock signal according to the control current.

A sampling circuit uses an input stage to sample an input signal and a secondary evaluation stage to maintain the output state of the input stage. Once the input stage transitions at a clock transition, the secondary evaluation stage uses regenerative feedback devices to hold the state to help ensure the sampling circuit only switches once during an evaluation.

An oscillator circuit includes: a plurality of delay elements, a first delay element configured to receive a first oscillator signal outputted from a second delay element in one stage before the first delay element and a second oscillator signal outputted from a third delay element in two or more stages before the first delay element, the plurality of delay terminals being connected in a ring by at least three or more delay elements, and the first oscillator signal and the second oscillator signal having phases different from one another; and a bias voltage generator configured to change a ratio of a first input bias current for the first oscillator signal to a second input bias current for the second oscillator signal, in accordance with a first bias voltage and a second bias voltage supplied to the plurality of delay elements.