A device and method for controllably delaying an electrical signal includes a first signal transfer path between a signal input and a signal output. The first signal transfer path includes a first signal transfer stage with a first differential pair and a common, adjustable first quiescent current source, and a second signal transfer path between the signal input and the signal output. The second signal transfer path includes a second signal transfer stage with a second differential pair and a common, adjustable second quiescent current source. An internal delay stage is arranged between the signal input and the second signal transfer stage and has a third differential pair and a common, adjustable third quiescent current source, and signal combination stage for additively superimposing the electrical signal transferred via the first signal transfer path on to the electrical signal transferred via the second signal transfer path.

A voltage-controlled ring oscillator (VCRO) and a VCRO-based sigma delta modulator having capability of enabling and disabling the VCRO cells. A VCRO includes a plurality of inverters coupled in a ring and a transition detector. The transition detector detects a transition of a first inverter and sends a control signal to enable a second inverter if the transition of the first inverter is detected. The transition detector may include a comparator configured to compare an input and an output of an inverter(s) to detect the transition of the first inverter and a latch configured to hold the control signal until it is reset.

A ring oscillator includes at least one oscillator stage having a first output and a second output and a start-up circuit. The start-up circuit includes a plurality of AC coupling capacitors receiving the first output and the second output, and a plurality of switches connected to the AC coupling capacitors. The start-up circuit is configured to provide a differential start-up voltage to at least one node of the oscillator using the plurality of switches and the AC coupling capacitors.

A ring voltage controlled oscillator (VCO) circuit is herein provided. According to one embodiment, a ring VCO circuit includes a plurality of stages connected in series, wherein each stage includes a first inverter, a second inverter, a third inverter and a fourth inverter, the first inverter connected in parallel with the third and fourth inverters and the second inverter connected in parallel with the third and fourth inverters, and a first biasing resistor connected to a first node and coupled to an input of the first inverter. The first biasing resistor includes a first switch configured to set the first biasing resistor to about zero voltage

A system, method and electronic device are provided. The system includes a shared fractional-N phase-lock loop (PLL), a ring oscillator circuit (OSC), and a multiphase injection pulse generator configured to receive an input signal having a first frequency from the shared fraction-N PLL and generate injection pulses for the OSC based on the input signal.

Methods and systems are described for generating multiple phases of a local clock at a controllable variable frequency, using loop-connected strings of active circuit elements. A specific embodiment incorporates a loop of four active circuit elements, each element providing true and complement outputs that are cross-coupled to maintain a fixed phase relationship, and feed-forward connections at each loop node to facilitate high frequency operation. A particular physical layout is described that maximizes operating frequency and minimizes clock pertubations caused by unbalanced or asymmetric signal paths and parasitic node capacitances.

A ring oscillator includes at least one oscillator stage having a first output and a second output and a start-up circuit. The start-up circuit includes a plurality of AC coupling capacitors receiving the first output and the second output, and a plurality of switches connected to the AC coupling capacitors. The start-up circuit is configured to provide a differential start-up voltage to at least one node of the oscillator using the plurality of switches and the AC coupling capacitors.

The present disclosure includes a frequency divider circuit that includes a superharmonically injection-locked ring oscillator, injection circuitry, and various switches. The input can include a collection of signal components at different phases that are all at the same, but changeable, frequency. The divider's division ratio can be changed during the divider's operation by, for example, utilizing one or more switches to change: the number of stages in the ring oscillator, and/or which stage(s) of the ring oscillator are injected into by which input signal components.

An apparatus for radio-frequency (RF) oscillation signal production is disclosed. In example implementations, an apparatus includes an oscillator. The oscillator includes multiple oscillation stages that are coupled together in series into a ring. A respective oscillation stage of the multiple oscillation stages includes a transconductance amplifier and a core oscillator. The transconductance amplifier is coupled to a preceding oscillation stage. The core oscillator is coupled to the transconductance amplifier and to a succeeding oscillation stage, with the core oscillator including at least one output node configured to provide a respective output signal. In some implementations, at least one capacitor is coupled across at least the transconductance amplifier. In some aspects, at least one transistor of the transconductance amplifier is implemented with a silicon-on-insulator metal-oxide-semiconductor (SOI MOS) device that includes at least one back-gate terminal.

Described are apparatus and methods for high frequency clock generation. A circuit includes a phase frequency detector (PFD) which outputs differential error clocks based on comparison of differential reference clocks and differential feedback clocks, which are at a first frequency. A controlled oscillator (CO) connected to the PFD, which adjusts a frequency of the CO based on the differential error clocks to generate differential clocks at a second frequency, which is a multiple of the first frequency. A quadrature clock generator connected to the CO, which generates differential quadrature clocks at the second frequency from the differential clocks, where the differential feedback clocks are generated from the differential clocks and one pair of the differential quadrature clocks. A frequency doubler which doubles each pair of the differential quadrature clocks and outputs fully differential and balanced clocks at a third frequency for distribution, which is a multiple of the second frequency.