The disclosure relates to a data level shifter circuit including a boost circuit configured to generate a boosted input data signal based on a transition of an input data signal; a first input transistor including a first control signal configured to receive the input data signal; a second input transistor including a second control terminal configured to receive the boosted input data signal, wherein the first and second input transistors are coupled in parallel between a node and a lower voltage rail; and a latch circuit configured to generate an output data signal based on the input data signal, wherein the latch circuit is coupled between an upper voltage rail and the node.

A voltage driver circuit for an output stage of an operational amplifier, or other circuits, includes a level shifter and an output driver including a source follower and a common source amplifier in a push-pull configuration. The level shifter generates a node voltage as a function of an input voltage on the input node. The output driver including a first transistor having a control terminal receiving the node voltage, and connected between a supply voltage and an output node, and a second transistor having a control terminal receiving the input voltage from the input node, and connected between the output node and a reference voltage, wherein the first and second transistors have a common conductivity type.

Provided are a device for adjusting an ultrasonic resonance frequency and a method of controlling the same. A device according to an embodiment of the present disclosure includes a circuit board configured to determine and output a resonance frequency. In addition, the device includes a frequency adjustor connected to at least one of a plurality of circuits mounted on the circuit board.

A latch circuit includes first and second NAND circuits and first and second capacitive elements. The first NAND circuit has a first input node into which a first signal is input. The second NAND circuit has a first input node into which a second signal is input, a second input node which is connected to an output node of the first NAND circuit, and an output node which is connected to a second input node of the first NAND circuit. The first capacitive element has one end connected to the first input node of the first NAND circuit and has another end connected to the output node of the first NAND circuit. The second capacitive element has one end connected to the first input node of the second NAND circuit and has another end connected to the output node of the second NAND circuit.

A receiving device may include a buffer, a summer circuit, a first delay cell, and a second delay cell. The buffer may receive an external signal. The summer circuit may sum an output of the buffer, a first feedback signal, and a second feedback signal. The first delay cell may generate the first feedback signal by delaying an output of the summer circuit. The second delay cell may generate the second feedback signal by delaying the first feedback signal. The delay amounts of the first and second delay cells may be set based on a delay control voltage.

The present document describes a voltage comparator (100) which comprises a differential stage (110) configured to provide a comparator current (203) at an output node (103) of the differential stage (110) in dependence of a first input voltage at a first input node (101) and a second input voltage at a second input node (102) of the voltage comparator (100). The voltage comparator (100) further comprises a current comparator (200) which is configured to provide an output voltage at an output node (206) of the current comparator (200) in dependence of the comparator current (203), and an output stage (220) which is configured to provide an output signal of the voltage comparator (100) in dependence of the output voltage at the output node (206) of the current comparator (200).

An input part is supplied with a low voltage from a low voltage power supply line. A level shift part and an output part are supplied with a high voltage from a high voltage power supply line. An input terminal is pulled up by a resistor and connected to the level shift part through a buffer circuit and an inverter circuit. The level shift part is connected in series with an NMOS and turned on when the input terminal changes to a low level. The output terminal is pulled up by a resistor through the buffer circuit. Even when the level shift part operates unstably because of long delay time from rising of a potential of the high voltage power supply line to rising of a potential of the low voltage power supply line, the output voltage is maintained at a high level.

An input part is supplied with a low voltage from a low voltage power supply line. A level shift part and an output part are supplied with a high voltage from a high voltage power supply line. An input terminal is pulled up by a resistor and connected to the level shift part through a buffer circuit and an inverter circuit. The level shift part is connected in series with an NMOS and turned on when the input terminal changes to a low level. The output terminal is pulled up by a resistor through the buffer circuit. Even when the level shift part operates unstably because of long delay time from rising of a potential of the high voltage power supply line to rising of a potential of the low voltage power supply line, the output voltage is maintained at a high level.

According to one embodiment, an input circuit is provided that inputs a voltage to each of drive terminals of a pair of differential transistors constituting a differential pair. The input circuit includes: a first input wiring section to which a first voltage is applied; a second input wiring section to which a second voltage; a first output wiring section to which a voltage is output to one of the pair of differential transistors; a second output wiring section to which a voltage is output to the other of the pair of differential transistors; a voltage generation circuit section that generates a third voltage based on at least one of the first voltage and the second voltage; a first transistor disposed between the first input wiring section and the first output wiring section; and a second transistor disposed between the second input wiring section and the second output wiring section.

A voltage comparator includes a differential stage configured to provide a comparator current at an output node of the differential stage in dependence of a first input voltage at a first input node and a second input voltage at a second input node of the voltage comparator. The voltage comparator further includes a current comparator which is configured to provide an output voltage at an output node of the current comparator in dependence of the comparator current, and an output stage which is configured to provide an output signal of the voltage comparator in dependence of the output voltage at the output node of the current comparator.