An integrated circuit including a first active region and a second active region extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; a power rail and a ground rail extending in the first direction and spaced apart from the first and second active regions and each other in the second direction; source/drain contacts extending in the second direction on at least a portion of the first or second active region, gate structures extending in the second direction and on at least a portion of the first and second active regions, a power rail configured to supply power through source/drain contact vias, and a ground rail configured to supply a ground voltage through source/drain contact vias.

The present document relates to a level shifter circuit configured to transform an input voltage at an input of the level shifter circuit into an output voltage at an output of the level shifter circuit. The level shifter circuit may comprise a first switching element coupled between an output supply voltage and a positive output terminal, wherein a control terminal of the first switching element is coupled to a negative output terminal. The level shifter circuit may comprise a second switching element coupled between the output supply voltage and the negative output terminal, wherein a control terminal of the second switching element is coupled to the positive output terminal. The level shifter circuit may comprise a drive circuit configured to drive the control terminals of the first and the second switching element based on the input voltage at the input of the level shifter circuit.

A voltage level shifter cell, which is configured to convert voltage levels of input signals of multi-bits, includes: a first circuit area including a first voltage level shifter configured to convert a 1-bit first input signal from among the input signals; and a second circuit area including a second voltage level shifter configured to convert a 1-bit second input signal from among the input signals, wherein the first circuit area and the second circuit area share a first N-well to which a first power voltage is applied, and the first circuit area and the second circuit area share a second N-well to which a second power voltage is applied, wherein the first N-well is formed to extend in a first direction, and the first N-well and the second N-well are arranged to overlap in a second direction crossing the first direction.

A data receiving circuit is provided. The data receiving circuit includes a first transistor, a second transistor, a third transistor, and a latch circuit. The first transistor has a gate configured to receive an input signal. The latch circuit is configured to output an output signal in response to the input signal. The second transistor has a gate configured to receive a first signal and a drain connected to the latch circuit. The third transistor has a gate configured to receive the first signal and a drain connected to the latch circuit. The second transistor and the third transistor are configured to provide a current to the latch circuit in response to the first signal.

A multi-chip package includes: a first semiconductor integrated-circuit (IC) chip; a second semiconductor integrated-circuit (IC) chip over and bonded to the first semiconductor integrated-circuit (IC) chip; a plurality of first metal posts over and coupling to the first semiconductor integrated-circuit (IC) chip, wherein the plurality of first metal posts are in a space beyond and extending from a sidewall of the second semiconductor integrated-circuit (IC) chip; and a first polymer layer over the first semiconductor integrated-circuit (IC) chip and in the space, wherein the plurality of first metal posts are in the first polymer layer, wherein a top surface of the first polymer layer, a top surface of the second semiconductor integrated-circuit (IC) chip and a top surface of each of the plurality of first metal posts are coplanar.

An artificial neuron includes a first capacitive node of application of a membrane potential of the neuron. A first transistor is configured to discharge the first capacitive node. A second capacitive node is driven according to the membrane potential and delivers a potential for controlling the first transistor. A second transistor is configured to discharge the second capacitive node. The second transistor is controlled according to a potential present at the second capacitive node.

A data receiving circuit is provided. The data receiving circuit includes a data input circuit, a latch circuit, and a current source. The data input circuit is configured to receive an input signal. The latch circuit is configured to output an output signal in response to the input signal. The current source is configured to provide a current to the latch circuit. The current source is different from the data input circuit.

Disclosed herein are non-limiting examples of charge pumps that reduce the introduction of noise into a circuit in which they are implemented and/or lower the output impedance when providing certain voltages (e.g., negative voltage generators). The disclosed technologies utilize a plurality of smaller charge pumps (or charge pump units) working in parallel that operate on different clock phases rather than using a single charge pump with a relatively large flying capacitor or a plurality of charge pumps in series. This can, for example, reduce spurious signals or spurs that arise due at least in part to the characteristics of the clock signal. The disclosed technologies may be particularly advantageous for SOI-based components and circuits.

A circuit includes: a first swing reduction circuit coupled between an input/output pad and a buffer circuit, and a second swing reduction circuit coupled between the input/output pad and the buffer circuit. The first swing reduction circuit comprises a first transistor gated by a first bias voltage and comprises a second transistor drained by the first bias voltage. The first swing reduction circuit is configured to increase a voltage at a first node in the buffer circuit when a voltage applied on the input/output pad is equal to a first supply voltage. The second swing reduction circuit is configured to reduce a voltage at a second node in the buffer circuit when the voltage applied on the input/output pad is equal to a second supply voltage.

An output driving circuit includes a pull-down driver and a voltage stabilizer. The pull-down driver includes first, second, and third transistors connected in series between a pad and a ground node. The voltage stabilizer generates a stabilization voltage based on a voltage of the pad and a power voltage, and outputs the stabilization voltage to a control terminal of the second transistor.