In certain aspects of the disclosure, an apparatus comprises a latching element having a data input, a first feedback input, a second feedback input, and an output. A pull-up input block is coupled to the data input and has at least a first pull-up input, and a pull-down input block is also coupled to the data input and has at least a first pull-down input. A feedback pull-down block implementing a logic function complementary to the pull-up input block is coupled to a feedback pull-down control device and responsive to the first pull-up input, and a feedback pull-up block implementing a logic function complementary to the pull-down input block is coupled to a feedback pull-up control device and responsive to the first pull-down input. The pull-up input block and pull-down input block are guaranteed not to be enabled concurrently.

In examples, an apparatus comprises a pin, an input buffer coupled to the pin at an output of the input buffer, a voltage divider circuit coupled to the input buffer at an input of the input buffer, a first current mirror coupled to the input buffer, and a second current mirror coupled to the input buffer. The apparatus also comprises a first output buffer coupled between the input buffer and the first current mirror, and a second output buffer coupled between the input buffer and the second current mirror.

Reduction in power consumption of a semiconductor device is achieved. The semiconductor device includes: a first circuit operating at a first power supply voltage and a second circuit operating at a second power supply voltage and including a level shift unit and a switch unit, the first circuit is configured of a low-breakdown-voltage n-type transistor that is an SOTB transistor, and the switch unit is configured of an n-type transistor that is an SOTB transistor. A second power supply voltage is higher than a first power supply voltage, and an impurity concentration of a channel formation region of the n-type transistor is higher than an impurity concentration of a channel formation region of the low-breakdown-voltage n-type transistor.

A level-shifting circuit includes a first supply terminal configured to receive a first supply voltage, a second supply terminal configured to receive a second supply voltage different from the first supply voltage, an input terminal of the level-shifting circuit configured to receive a voltage having a first voltage level, and an output terminal of the level-shifting circuit. The level-shifting circuit can include a shifting circuit having electrical connections to the input terminal and the output terminal and configured to, in response to a first voltage at a first node, produce a second voltage at a second node. The level-shifting circuit can also include a feedback circuit and a clamping circuit configured to limit leakage current.

A level shifter with reduced propagation delay. A level shifter includes a signal input terminal, a first signal output node, a first transistor, a second transistor, a third transistor, and a first capacitor. The first transistor includes a control terminal coupled to the signal input terminal. The second transistor includes an output terminal coupled to an input terminal of the first transistor. The first capacitor includes a bottom plate coupled to an input terminal of the second transistor. The third transistor includes a control terminal coupled to a top plate of the first capacitor, and an output terminal coupled to the first signal output node.

A level-shifting circuit includes a first supply terminal configured to receive a first supply voltage, a second supply terminal configured to receive a second supply voltage different from the first supply voltage, an input terminal of the level-shifting circuit configured to receive a voltage having a first voltage level, and an output terminal of the level-shifting circuit. The level-shifting circuit can include a shifting circuit having electrical connections to the input terminal and the output terminal and configured to, in response to a first voltage at a first node, produce a second voltage at a second node. The level-shifting circuit can also include a feedback circuit and a clamping circuit configured to limit leakage current.

A high voltage level shifting circuit and related semiconductor devices are presented. The circuit comprises: a level conversion circuit that converts an input signal with a first high voltage to an output signal with a second high voltage; a first switch having a first node connected to a first power source and a second node connected to a control node of a first transistor; a second switch having a first node connected to the control node of the first transistor and a second node connected to a first connection node; and a switch control circuit connected to the first switch and the second switch and controls them not to be close at the same time. By adding these two switches to the level conversion circuit, this inventive concept substantially lowers the static current generated during a high voltage level conversion process.

The present technology relates to a semiconductor device that includes a level shifter circuit that performs level conversion on a digital signal output from a predetermined block and outputs a resultant signal to another block that operates by a power source different from the power source of the predetermined block, and a power source monitoring circuit that controls an operation of the level shifter circuit. The power source monitoring circuit stops an operation of the level shifter circuit on the basis of a status of the power source that supplies power to the predetermined block and a standby control signal for controlling an operation status of the other block. Further, the power source monitoring circuit is provided with a transistor on a path of a steady-state current, and the steady-state current is inhibited from flowing in accordance with the standby control signal.

A regeneration circuit includes a first inverting circuit, a second inverting circuit, a first transistor coupled to an input of the second inverting circuit, and a second transistor coupled to an input of the first inverting circuit. The regeneration circuit also includes a third transistor including a gate coupled to a gate of the first transistor, a first switch configured to couple the third transistor to the input of the second inverting circuit based on a voltage of the first inverting circuit, a fourth transistor including a gate coupled to a gate of the second transistor, and a second switch configured to couple the fourth transistor to the input of the first inverting circuit based on a voltage of the second inverting circuit.

A level-shifting circuits utilizing storage cells for shifting signals low-to-high or high-to-low include control drivers with moving supply voltages. The moving supply voltages may power positive or negative supply terminals of the control drivers. The control drivers drive gates of common-source configured devices coupled to storage nodes of the storage cell.