A digital level shifter adapted to shift an input signal from switching in a low voltage range, to an output switching in a high voltage range has a glitch generator configured to generate pulses at rising and falling transitions of the input signal. Glitch generator output triggers a multiple-level current source to a high current mode, operating in a low current mode at other times. The current source feeds a differential pair of high voltage transistors with a first transistor of the pair having a gate coupled to the input signal and a second transistor of the pair having a gate coupled to a complement of the input signal. An active load and buffer circuit receives current from the differential pair and drives the output accordingly.

In an example, a level shifter includes a low side having first and second inputs. The level shifter also includes a high side, where the high side has a latch having first and second terminals. The high side also includes a current comparator including first and second current mirrors. The high side includes isolation circuitry including first and second transistors, in which the first transistor has a first control terminal, the second transistor has a second control terminal, the first transistor is coupled between the first terminal and the first current mirror, the second transistor is coupled between the second terminal and the second current mirror, the first control terminal is coupled to the second current mirror, and the second control terminal is coupled to the first current mirror.

A dynamic flip-flop circuit with a feedback loop includes a input tristate circuit configured to receive a data signal and a clock signal to output a tristate output data signal. The dynamic flip-flop circuit also includes a feedforward circuit configured to receive the tristate output data signal as input to output a feedforward output data signal. The dynamic flip-flop circuit also includes a feedback loop circuit configured to connect the output of the feedforward circuit and the output of the input tristate circuit. The feedback loop circuit includes a transmission gate circuit that is partially on.

An input circuit receives an input voltage and generates a digital output. A first signal splitter generates a lower signal which tracks the input voltage in a range of a first voltage level and a second voltage level and provides a first control signal based on the upper signal. A second signal splitter generates an upper signal which tracks the input voltage in a range of the second voltage level and a third voltage level and provides at least one control signal based on the upper signal. The third voltage level is greater than the second voltage level which is greater than the first voltage level. A level shifter receives the at least one control signal from the second signal splitter and provides a third control signal, and a combiner circuit generates the digital output as a logical combination of the first and third controls signals.

A level shifter is disclosed. The input circuit receives an input signal operating within a first voltage range that is defined by a first voltage level. A pull-up circuit is coupled between a second voltage line and the input circuit. The second voltage line supplies a second voltage level. The second voltage level is higher than the first voltage level. A first connection node between the pull-up circuit and the input circuit serves as an output terminal of the level shifter. An acceleration circuit coupled to the first connection node accelerates the low-to-high transition at the output terminal. The acceleration controller for the acceleration circuit includes a first series of pulse generation transistors driven by first driving signals which have time differences therebetween, so that the acceleration controller enables the acceleration circuit in a pulse manner. The first driving signals are derived from the input signal.

An input circuit receives an input voltage and generates a digital output. A first signal splitter generates a lower signal which tracks the input voltage in a range of a first voltage level and a second voltage level and provides a first control signal based on the upper signal. A second signal splitter generates an upper signal which tracks the input voltage in a range of the second voltage level and a third voltage level and provides at least one control signal based on the upper signal. The third voltage level is greater than the second voltage level which is greater than the first voltage level. A level shifter receives the at least one control signal from the second signal splitter and provides a third control signal, and a combiner circuit generates the digital output as a logical combination of the first and third controls signals.