A level-shifter circuit operates to shift an input signal referenced to a first set supply voltages to generate an output signal referenced to a second set of supply voltages. The output signal from the level-shifter circuit is latched by a latching circuit. A logic gate has a first input configured to receive the input signal, a second input configured to receive a feedback signal and an output coupled to a input of the level shifting circuit. A feedback circuit has a first input configured to receive the output signal, a second input configured to receive the input signal and an output configured to generate the feedback signal. The feedback circuit operates to sense an uncontrolled switching event of the output signal occurring in the absence of a switching of the input signal and apply, in response thereto, the feedback signal to cancel the uncontrolled switching event.

A level shifter includes (a) an input unit including (i) a first input transistor configured to receive a first voltage and connected to a first connection node, and (ii) a second input transistor configured to receive the first voltage and connected to a second connection node, (b) an output unit including (i) a first output transistor connected to a first output terminal and configured to receive a second voltage, and (ii) a second output transistor connected to a second output terminal and configured to receive the second voltage, (c) a first bias unit configured to control voltage drop between the output terminals and the connection nodes based on a first bias signal, and (d) a second bias unit configured to control a first voltage drop between the first output transistor and the second output terminal and a second voltage drop between the second output transistor and the first output terminal based on a second bias signal.

A receiver circuit receives a signal from a semiconductor device. The receiver circuit includes an input buffer including a first plurality of transistors, the input buffer being configured to detect a fabrication condition of the receiver circuit, generate a control signal according to the detected fabrication condition, and control a gain of an input signal by adjusting a number of operating transistors among the first plurality of transistors in response to the control signal; and a latch circuit configured to latch an output signal of the input buffer, and adjust threshold voltages of a second plurality of transistors in response to a test signal.

A high-speed low-power-consumption trigger, which comprises a control signal generation circuit, an enabling unit, and a latch structure. The latch structure comprises two input ends, two output ends, two enabling ends, a second enabling end, and a ground end. The enabling unit comprises two enabling circuits. An output signal X of the control signal generation circuit and an external control signal D serve as input signals of the first enabling circuit. An output end of the first enabling circuit is connected to the first enabling end. The output signal X of the control signal generation circuit and a phase-inverted signal DB of the external control signal D serve as input signals of the second enabling circuit. An output end of the second enabling circuit is connected to the second enabling end.

A level shifter circuit which includes a cross-coupled latch and a set-reset latch is introduced. The level shifter circuit includes a first input node, a second input node and a plurality of switches. The first input node and the second input node are configured to receive a first digital input signal and a second digital input signal, respectively. The plurality of switches are configured to be switched on or off according to at least one control signal to output a first output signal and a second output signal. The set-reset latch is coupled to the cross-coupled latch and includes a set input node, a reset input node and an output node. The set input node and the reset input node are configured to receive the first output signal and the second output signal of the cross-coupled latch, respectively. The output node outputs a level-shifted output signal according to the first output signal and the second output signal of the cross-coupled latch. A method adapted to a level shifter circuit is also introduced.

Apparatuses for receiving an input data signal are described. An example apparatus includes: a plurality of data input circuits and an internal data strobe generator. Each data input circuit of the plurality of data input circuits includes: an amplifier that receives data from a data terminal, and latches the data in an enable state and refrains from latching data in a disable state; and a voltage control circuit coupled to a tail node of the amplifier and provides a first voltage to the tail node during the enable state, and further provides a second voltage different from the first voltage to the tail node in a first mode and to sets the tail node in a floating state in a second mode during the disable state. The internal data strobe signal generator provides a plurality of internal data strobe signals to the plurality of corresponding data input circuits respectively.

A level shift circuit includes: a constant-current generation unit; a current mirror unit that flows the constant-current through first and second lines; and a level shift unit that receives first and second input signals, the first input signal being varied between first and second logic levels and having first and second potentials at the first and second logic levels respectively, the second input signal being a phase-inverted signal of the first input signal, the level shift unit producing first and second output signals that are acquired by shifting a signal level at the first logic level of the first and second input signals from the first potential to the power supply potential, the level shift unit outputting the first output signal from a node on the second line and outputting the second output signal from a node on the first line. The constant-current generation unit includes a current adjustment circuit which varies the constant current value depending on a variation in the first potential.

A flip-flop includes a first node charging circuit configured to charge a first node with inverted input data generated by inverting input data, a second node charging circuit configured to charge a second node with the input data, and first through eighth NMOS transistors. The flip-flop is configured to latch the input data at rising edges of a clock signal and output latched input data as output data. The flip-flop includes an internal circuit configured to charge a sixth node with inverted input data generated by inverting the latched input data.

A level shifter includes a buffer circuit, a first shift circuit, and a second shift circuit. The buffer circuit provides a first signal and a first inverted signal to the first shift circuit, such that the first shift circuit provides a second signal and a second inverted signal to the second shift circuit. The second shift circuit generates a plurality of output signals according to the second signal and the second inverted signal. The first shift circuit includes a plurality of first stacking transistors and a first voltage divider circuit. The first voltage divider circuit is electrically coupled between a first system high voltage terminal and a system low voltage terminal. The first voltage divider circuit is configured to provide a first inner bias to gate terminals of the first stacking transistors.

A method and system of the branch look-ahead (BLA) instruction disassembling, assembling, and delivering are designed for improving speed of branch prediction and instruction fetch of microprocessor systems by reducing the amount of clock cycles required to deliver branch instructions to a branch predictor located inside the microprocessors. The invention is also designed for reducing run-length of the instructions found between branch instructions by disassembling the instructions in a basic block as a BLA instruction and a single or plurality of non-BLA instructions from the software/assembly program. The invention is also designed for dynamically reassembling the BLA and the non-BLA instructions and delivering them to a single or plurality of microprocessors in a compatible sequence. In particular, the reassembled instructions are concurrently delivered to a single or plurality of microprocessors in a timely and precise manner while providing compatibility of the software/assembly program.