To provide a miniaturized data holding circuit. First and second MOS transistors respectively transmit a data signal and an inverted data signal to inputs of first and second inverting gates that constitute a state holding circuit when a clock signal is at a first level. Fifth and sixth MOS transistors are respectively inserted in a feedback path from an output of the second inverting gate to the input of the first inverting gate and a feedback path from an output of the first inverting gate to the input of the second inverting gate, and respectively transmit the outputs of the second and first inverting gates when the clock signal is at a second signal level. Seventh and eighth MOS transistors are constituted in a channel of a conductive type different from the first MOS transistor and connected in parallel to the fifth and sixth MOS transistors, respectively, and transmit the output of the second inverting gate and the output of the first inverting gate on the basis of the inverted data signal and the data signal, respectively.

A level shifter circuit is provided. In some examples, the level shifter circuit includes a first set of transistors and a second set of transistors coupled between first and second power supply nodes. The control terminals of the first and second lower transistors are coupled to an input node. The level shifter circuit also includes a third set of transistors and a fourth set of transistors coupled between first and third power supply nodes. A control terminal of a third lower transistor is coupled to a second intermediate node, and a control terminal of a fourth lower transistor is coupled to a first intermediate node. Control terminals of the first upper transistor and the fourth upper transistor are coupled to a third intermediate node. Control terminals of the second upper transistor and the third upper transistor are coupled to a fourth intermediate node.

Circuits integrating OR logic and level shifting functionality and methods of operating the same are configured to accommodate different applications. One such circuit comprises first and second transistors coupled in parallel defining first and second nodes, the first transistor being responsive to a first input signal and the second transistor being responsive to a second input signal; a first resistor coupled between a power supply terminal of the circuit and the first node; and a second resistor coupled between the second node and a ground terminal of the circuit. The circuit generates an output signal having a voltage level that is lower than a voltage level of each of the first and second input signals.

A level shifter includes an input circuit having first and second input terminals configured to receive complementary input signals at a first voltage level and a second voltage level. A cross-latch circuit is coupled to the input circuit, and has first and second output terminals configured to provide complementary output signals at a third voltage level and a fourth voltage level. The input circuit includes first and second control nodes configured to output first and second control signals at the first voltage level and the fourth voltage level based on the input signals. A tracking circuit is coupled to the input circuit and the cross-latch circuit, and is configured to input first and second tracking signals to the cross-latch circuit based on the first and second control signals, wherein the first tracking signal is the greater of the first control signal and the third voltage level, and the second tracking signal is the greater of the second control signal and the third voltage level.

A method includes: forming first, second, and third NWs; forming form first to fourth transistors in corresponding first to fourth groups of active regions, connecting selected transistors amongst the first and second transistors to form first and second input circuits respectively receiving a first input signal in a first domain and a second input signal in the first domain; connecting selected transistors amongst the first and third transistors and amongst the first and fourth transistors to respectively form a first single bit level shifter (SBLS) and a second SBLS; each SBLS operates in the second domain and receives correspondingly versions of the first and second input signals; and connecting selected transistors amongst the first and third transistors to form a control circuit for toggling the first and second SBLSs between a normal and a standby state, a portion of the control circuit and the first SBLS sharing the second NW.

A method includes: forming first, second, and third NWs; forming form first to fourth transistors in corresponding first to fourth groups of active regions, connecting selected transistors amongst the first and second transistors to form first and second input circuits respectively receiving a first input signal in a first domain and a second input signal in the first domain; connecting selected transistors amongst the first and third transistors and amongst the first and fourth transistors to respectively form a first single bit level shifter (SBLS) and a second SBLS; each SBLS operates in the second domain and receives correspondingly versions of the first and second input signals; and connecting selected transistors amongst the first and third transistors to form a control circuit for toggling the first and second SBLSs between a normal and a standby state, a portion of the control circuit and the first SBLS sharing the second NW.

A circuit includes an input circuit, a level shifter circuit, an output circuit, and a first and a second feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second input signal. The level shifter circuit is coupled to a second voltage supply, and configured to generate at least a first and second signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the second voltage supply, and configured to generate at least an output signal, a first and second feedback signal responsive to the first signal. The first and second feedback circuit are configured to receive the enable signal, and the inverted enable signal, and the corresponding first and second feedback signal.

A level shifting circuit includes negative voltage shifting circuitry including a first leg and a second leg. The first leg includes a first NMOS transistor and a first PMOS transistor in series with a first input node and a negative amplified voltage, and the second leg includes a second NMOS transistor and a second PMOS transistor in series with a second input node and the negative amplified voltage. The level shifting circuit further includes positive voltage shifting circuitry including a first plurality of high voltage transistors in series with a positive amplified voltage and an output node of the level shifting circuit, and a second plurality of high voltage transistors in series with a first intermediate node of the first leg of the negative voltage shifting circuitry and the output node of the level shifting circuit. The level shifting circuitry further includes input circuitry including a plurality of inverters.

A level shifter circuit is provided. In some examples, the level shifter circuit includes a first set of transistors and a second set of transistors coupled between first and second power supply nodes. The control terminals of the first and second lower transistors are coupled to an input node. The level shifter circuit also includes a third set of transistors and a fourth set of transistors coupled between first and third power supply nodes. A control terminal of a third lower transistor is coupled to a second intermediate node, and a control terminal of a fourth lower transistor is coupled to a first intermediate node. Control terminals of the first upper transistor and the fourth upper transistor are coupled to a third intermediate node. Control terminals of the second upper transistor and the third upper transistor are coupled to a fourth intermediate node.

A multi-bit level-shifter (MBLS) includes two or more input circuits correspondingly configured to operate in a first voltage domain. The MBLS also includes two or more single bit level shifters (SBLSs) electrically coupled correspondingly to the two or more input circuits, and correspondingly configured to operate in a second voltage domain. The MBLS also includes a control circuit configured to toggle each of the two or more SBLSs between a normal mode and a standby mode according to a toggle-control signal received from the control circuit.