A circuit includes first and second power domains. The first power domain has a first power supply voltage level and includes a master latch, a first level shifter, and a slave latch coupled between the master latch and the first level shifter. The second power domain has a second power supply voltage level different from the first power supply voltage level and includes a retention latch coupled between the slave latch and the first level shifter, and the retention latch includes a second level shifter.

A semiconductor device may include a master latch that stores an input data signal, using a local power supply voltage and a clock signal, and outputs the input data signal to a first output signal; a slave latch that stores the first output signal, using a global power supply voltage, the clock signal and a retention signal, and outputs a second output signal; a first logic gate that receives input of one signal and another signal of the retention signal, the clock signal and the reset signal, and outputs a first control signal generated by performing a first logical operation; and a second logic gate that receives input of the rest of the retention signal, the clock signal and the reset signal, and the first control signal, and performs a second logical operation to at least one of the master latch and the slave latch.

Provided is a semiconductor device including low power retention flip-flop. The semiconductor device includes a first line to which a global power supply voltage is applied, a second line to which a local power supply voltage is applied, the second line being separated from the first line, a first operating circuit connected to the second line to use the local power supply voltage, a first power gating circuit determining whether the local power supply voltage is applied to the first operating circuit and a first retention flip-flop connected to the first line and the second line, wherein the first retention flip-flop comprises a first circuit including a master latch, a second circuit including a slave latch, and a first tri-state inverter connected between the master latch and the slave latch.

Integrated circuits having flip-flops with asynchronous reset capabilities are provided. The flip-flops may be single event upset (SEU) hardened registers implemented using dual-interlocked cell (DICE) latch circuits. A logic gate may be inserted at the data input of each flip-flop. A multiplexer may be inserted at the input of the clock tree that is being used to feed clock signals to each of the flip-flops. Both the logic gate and the multiplexer may receive an asynchronous reset signal. The multiplexer may also receive a normal clock signal and a delayed clock pulse signal that is triggered in response to detecting assertion of the reset signal.

Tri-state inverter comprising: a n-TFET and a p-TFET, the drain of the n-TFET being connected to the drain of the p-TFET and to an output of the tri-state inverter, the gates of the n-TFET and p-TFET being connected to an input of the tri-state inverter; a control circuit able to apply a first control voltage on the source of the n-TFET and a second control voltage on the source of the p-TFET, the values of the first and second control voltages being positive or zero; and wherein, when the tri-state inverter is intended to work as an inverter, the value of the first control voltage is lower than the value of the second control voltage, and when the tri-state inverter is intended to be tri-stated, the value of the first control voltage is higher than the value of the second control voltage.

Embodiments of the present disclosure relate to a flip flop circuit that obviates the need of a transmission gate. The flip flop includes a first match multiplexer, a second match multiplexer and a separable inverter. The first match multiplexer receives an input data signal and generates a feedback output based on the input data signal and the logic levels at two nodes coupled to the first match multiplexer. The separable inverter receives the feedback output and switches the logic level of one of two nodes but maintains the logic level per each clock cycle. The second match multiplexer generates a signal output based on the logic levels at the two nodes and the signal output that is fed back into the second match multiplexer. Embodiments may reduce power consumption and operate at lower voltages.

A semiconductor device and a method of operating a semiconductor device are provided. The semiconductor device includes a first latching circuit and a second latching circuit coupled to the first latching circuit. The second latching circuit includes a first feedback circuit and a first transmission circuit, the first feedback circuit configured to receive a first clock signal of a first phase and a second clock signal of a second phase, and the first transmission circuit configured to receive the second clock signal and a third clock signal of a third phase. The first feedback circuit is configured to be turned off by the first clock signal and the second clock signal before the first transmission circuit is turned on by the second clock signal and the third clock signal.

A flip-flop with glitch protection is disclosed. The flip-flop includes a differential amplifier circuit that generates amplifier output signals based on an input data and clock signals and precharges a true data node when a clock signal is inactive. A latch circuit is coupled to the differential amplifier and includes a latch node. Responsive to a current value of the input data signal having a first logic state, the latch node is set at a logic value equivalent to the precharged value during an active phase of the clock signal. Responsive to the current value of the input data signal having a second logic state complementary to the first, during the active phase of the clock signal, the latch circuit causes the latch node to be set to a logic value complementary to the precharged value, using the clock signal and the current value of the input data signal.

An integrated circuit disclosed here includes a first plurality of cell rows, a second plurality of cell rows, first and second clock inverters, and a plurality of flip-flops. The second plurality of cell rows are arranged abutting the first plurality of cell rows. A first number of fins in the first plurality of cell rows is different from a second number of fins in the second plurality of cell rows. The first and second clock inverters are arranged in the second plurality of cell rows. The plurality of flip-flops are arranged in the first plurality of cell rows and the second plurality of cell rows. The plurality of flip-flops include a first plurality of flip-flops configured to operate in response to the first clock and second clock signals.

Disclosed is a semiconductor device including a substrate with first and second regions adjacent to each other in a first direction, and first to third gate electrodes extending from the first region toward the second region. Each of the first and second regions includes a PMOSFET region and an NMOSFET region. The first to third gate electrodes extend in the first direction and are sequentially arranged in a second direction different from the first direction. The first and third gate electrodes are supplied with a first signal. The second gate electrode is supplied with a second signal that is an inverted signal of the first signal. The first gate electrode includes a first gate of the first region and a first gate of the second region. The first gates are aligned and connected with each other in the first direction.