A temperature compensated oscillation circuit is provided. The temperature compensated oscillation circuit generates a first delay voltage and a second delay voltage according to the first resistance value. A first order term of a temperature change function of the first resistance value is eliminated. The temperature compensated oscillation circuit generates a reference voltage according to a first reference resistance value and a second reference resistance value. A first order term of a temperature change function of the first reference resistance value is set to equal to a first order term of a temperature change function of the second reference resistance value. The second reference resistance value is adjusted such that variation of the reference voltage matches a second order term of the temperature change function of the first resistance value, thereby providing a clock that does not vary due to a variation in temperature.

A temperature compensated oscillation circuit is provided. The temperature compensated oscillation circuit generates a first delay voltage and a second delay voltage according to the first resistance value. A first order term of a temperature change function of the first resistance value is eliminated. The temperature compensated oscillation circuit generates a reference voltage according to a first reference resistance value and a second reference resistance value. A first order term of a temperature change function of the first reference resistance value is set to equal to a first order term of a temperature change function of the second reference resistance value. The second reference resistance value is adjusted such that variation of the reference voltage matches a second order term of the temperature change function of the first resistance value, thereby providing a clock that does not vary due to a variation in temperature.

The present invention relates to a technology capable of compensating for a frequency error in a quadrature relaxation oscillator. The quadrature relaxation oscillator generates a signal at a desired frequency by using a resistor and a capacitor which are less sensitive to a PVT (Process, Voltage, Temperature) variation, generates a signal at a desired frequency by compensating for an error from design, which is caused by a mismatch between circuits due to a characteristic of a semiconductor process, through a feedback lop, and removes noise.

The present invention relates to a technology capable of compensating for a frequency error in a quadrature relaxation oscillator. The quadrature relaxation oscillator generates a signal at a desired frequency by using a resistor and a capacitor which are less sensitive to a PVT (Process, Voltage, Temperature) variation, generates a signal at a desired frequency by compensating for an error from design, which is caused by a mismatch between circuits due to a characteristic of a semiconductor process, through a feedback lop, and removes noise.

Integrated circuits having self-calibrating oscillators, and methods of operating the same are disclosed. A disclosed example integrated circuit includes a clock generator, a comparator having a first input connected to an output of the clock generator and a second input connected to a reference voltage, a calibration done detector having an input connected to an output of the comparator and an output communicatively coupled to a calibration code register.

An electronic circuit is configured to output an output signal after elapse of a predetermined time from a received trigger signal, and includes an oscillator configured to output a pulse signal having a predetermined oscillation frequency; a counter circuit configured to count the pulse signal from the oscillator upon receiving the trigger signal and to output the output signal in response to a count value reaching a predetermined value; and a trimming circuit including a plurality of trimming elements which includes a cuttable conductive part and configured to output a selection signal corresponding to a trimming element having a cut conductive part. In the trimming circuit, the trimming element, which corresponds to the oscillation frequency of the pulse signal output from the oscillator among the plurality of trimming elements, is cut, and the counter circuit is configured to set the predetermined value according to the selection signal.

Disclosed is a differential relaxation oscillator using a differential structure that may stably maintain a differential voltage swing of capacitors despite an influence of an offset voltage and 1/f noise of a comparator, and also generate a dynamic current only at a point in time at which switching is performed, thereby minimizing power consumption.

Disclosed is a differential relaxation oscillator using a differential structure that may stably maintain a differential voltage swing of capacitors despite an influence of an offset voltage and 1/f noise of a comparator, and also generate a dynamic current only at a point in time at which switching is performed, thereby minimizing power consumption.

A circuit generates a clock signal with a tunable clock period. The circuit comprises capacitors, first tuning circuitry and second tuning circuitry. The first tuning circuitry is configured to adjust the clock period with a first period tuning step based on a first parameter and the second tuning circuit is configured to adjust the clock period with a second period tuning step based on a second parameter. The first period tuning step is different than the second period tuning step.

A comparator-based oscillator generates an output frequency that is relatively independent of comparator offset voltages. Charging/discharging circuitry controls the comparator input voltage, and logic circuitry generates the oscillator output (e.g., clock) signal and controls the charging/discharging circuitry. During an oscillator charging cycle, the charging/discharging circuitry drives the voltage at the comparator input node from a relatively low initial charging voltage level up to the comparator reference voltage. During an oscillator discharging cycle, the charging/discharging circuitry drives the voltage at the comparator input node from a relatively high initial discharging voltage level down to the comparator reference voltage. The initial charging and discharging voltage levels depend on the comparator reference voltage, such that a comparator offset voltage directly affects the initial charging and discharging voltage levels, thereby keeping the output frequency relatively unchanged.