A system on chip (SOC) includes a power distribution network (PDN) that has two different types of power multiplexers. The first power multiplexer type includes a lower resistance switching logic, and the second type includes a higher resistance switching logic as well as digital logic to provide an enable signal to the first type of power multiplexer. A given first-type power multiplexer may have multiple power multiplexers of the second type in a loop, the loop including communication paths for the enable signal and feeding the enable signal back to an enable input of the first-type power multiplexer.

Some embodiments of the invention include a pre-pulse switching system. The pre-pulsing switching system may include: a power source configured to provide a voltage greater than 100 V; a pre-pulse switch coupled with the power source and configured to provide a pre-pulse having a pulse width of T.sub.pp; and a main switch coupled with the power source and configured to provide a main pulse such that an output pulse comprises a single pulse with negligible ringing. The pre-pulse may be provided to a load by closing the pre-pulse switch while the main switch is open. The main pulse may be provided to the load by closing the main switch after a delay T.sub.delay after the pre-pulse switch has been opened.

The present invention relates to a relay driving circuit and a battery system for generating a gate voltage for controlling ON/OFF of a pre-charge relay, and provides a relay driving circuit that controls electrical connection between an external device and a battery pack, including: a transistor that receives a control signal of an enable level to perform an ON operation; a first resistor having a first end connected to a positive electrode of the battery pack and a second end connected to the relay, by the ON operation of the transistor; and a second resistor connected between the the second end of the first resistor and the external device, the relay receives power supplied from the battery pack in a ratio of a resistance value of the second resistor to a sum resistance value of the first resistor and the second resistor to perform an ON operation.

The present disclosure provides a hot-swap circuit and a control apparatus. The hot-swap circuit includes: a power input terminal, a power output terminal; a startup module electrically connected to the power input terminal and the power output terminal; a switch module electrically connected to the power input terminal, the power output terminal, and the startup module; a detection module electrically connected to the startup module, the switch module, and the power output terminal. When a surge signal is input at the power input terminal, a voltage value of a first control signal output by the detection module doesn't fall in a voltage value range of a preset first control signal, then the switch module is controlled to be turned off, so as to cut off a power signal input to the power output terminal, reducing probability of circuit damage, and reducing sparking phenomena of hot-swap power interfaces.

A semiconductor device drive circuit includes a first drive circuit and a second drive circuit. The first drive circuit generates a control signal for controlling a voltage-controlled switching element. The first drive circuit generates a control signal in synchronization with a voltage signal input to the first drive signal. The first drive circuit has an output current capability corresponding to a magnitude of the voltage signal. The second drive circuit outputs a voltage signal to the first drive circuit. The second drive circuit includes an output adjustment circuit that adjusts the magnitude of the voltage signal.

Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

An aspect relates to an apparatus including a first and second power rails; a first set of power switch cells coupled to the first and second power rails, the first set of power switch cells being cascaded from an output to an input of a control circuit; and a second set of power switch cells coupled to the first and second power rails, the second set of power switch cells being coupled to one of a pair of cells of the first set, the first output, and the first input of the control circuit. Another aspect relates to a method including propagating a control signal via a first set of cascaded power switch cells to sequentially couple a first power rail to a second power rail; and propagating the control signal via a second set of power switch cells coupled between a pair of cells of the first set.

The present disclosure provides a debounced solid state switching device comprised of at least two insulated-gate bipolar transistors (“IGBTs”) within a parallel architecture. Multiple pairs of IGBTs may be used in a parallel architecture to extend ampacity and improve voltage withstand capability. The device provides improved flexibility and portability to facilitate time and cost efficiency, as the size and complexity of the device is directly dependent on the needs of the user. Furthermore, the procurement of the components of the device is simple, providing greater accessibility.

An embodiment of a semiconductor device comprises a transistor cell array in a semiconductor body. The transistor cell array comprises transistor cell units. Each of the transistor cell units comprises a control terminal and first and second load terminals, respectively. The transistor cell units are electrically connected in parallel, and the control terminals of the transistor cells units are electrically connected. A first group of the transistor cell units includes a first threshold voltage. A second group of the transistor cell units includes a second threshold voltage larger than the first threshold voltage. A channel width of a transistor cell unit of the first group is smaller than a channel width of a transistor cell unit of the second group.

A gate driving circuit of embodiments is provided with a first transistor which controls a gate-on voltage applied to a gate electrode of a switching device, a second transistor which controls a gate-off voltage applied to the gate electrode of the switching device, a driving logic circuit which controls turn-on/turn-off of the first and second transistors, a first power source which supplies the gate-on voltage to the gate electrode when the first transistor is turned on, a second power source which supplies the gate-off voltage to the gate electrode when the second transistor is turned on, a first gate resistance variable circuit in which a plurality of field effect transistors is connected in parallel, a second gate resistance variable circuit in which a plurality of field effect transistors is connected in parallel, and a gate resistance control circuit which controls gate voltages of a plurality of field effect transistors.