A semiconductor device connectable between a first power-supply line connected to a power source and through which power is continuously supplied to a first circuit, and a second power-supply line that is not directly connected to the power source and is connected to a second circuit, includes a first switch connectable between the first and second power-supply lines and turned on in response to a signal for supplying power to the second circuit, a second switch connectable between the first and second power-supply lines and having a current supply capability higher than the first switch, and a control circuit configured to turn on the second switch when the first switch is turned on and a voltage applied to the second power-supply line has reached a threshold.

A driver for a power field-effect transistor includes a first and second circuits that apply respective charge currents to a gate of the power field-effect transistor when a control signal has a first logic value and the voltage between the gate and the source is smaller than a first threshold voltage and greater than a second threshold voltage. Third and fourth circuits apply respective discharge currents to the gate when the control signal has a second logic value and the voltage between the gate and the source is greater than a third threshold voltage and smaller than a fourth threshold voltage. The driver may include at least one field-effect transistor configured to generate at least one of the first, second, third or fourth threshold voltage.

The invention relates to a method (200) and a control device (1) for controlling at least two power semiconductor switches (LHS1 . . . LHSn) connected in parallel for switching a total current (I_ges). The at least two power semiconductor switches (LHS1 . . . LHSn) connected in parallel each have a gate terminal for controlling the respective power semiconductor switch (LHS1 . . . LHS2). An input terminal (EA) for feeding the total current (I_ges), an output terminal (AA) for discharging the total current (I_ges) and a joint control terminal (S) for receiving a joint control signal (SI) that has the state ‘disconnect’ or ‘connect’ are provided. The at least two power semiconductor switches (LHS1 . . . LHSn) connected in parallel are connected to the input terminal (EA) at the input end and to the output terminal (AA) at the output end. At least one ascertainment unit (EE) is designed to receive the joint control signal (SI) at the input end, ascertain at least two individual control signals (SI1 . . . SIn) in accordance with the joint control signal (SI) in order to control the at least two power semiconductor switches (LHS1 . . . LHSn), and output the at least two ascertained individual control signals to the gate terminals of the at least two power semiconductor switches at the output end. The at least two individual control signals (SI1 . . . SIn) each have the state ‘disconnect’ or ‘connect’ and differ at least temporarily.

A switch including multiple current branches and slope circuitry. The slope circuitry activates or deactivates the current branches one at a time according to a corresponding one of multiple slope functions in response to a transition of the input signal. Each current branch develops a current so that the output node follows a predetermined voltage-current function. Each slope function is other than a step function and may be linear or non-linear. A slope function may be configured as a current-starved inverter charging or discharging a capacitor with a fixed current. Delay circuitry may be included to delay the inputs or the outputs of the slope circuitry configured as multiple slope control circuits. The slope control circuits may be daisy-chained from first to last to effectuate the delay. Each current branch may include an electronic switch and may further include a resistor to determine the current level.

A gate driver circuit includes at least one driver configured to generate a first gate control signal for a first power disconnect switch and a second gate control signal for a second power disconnect switch in parallel with the first power disconnect switch, and logic configured to implement a delayed turn on time for the second gate control signal compared to the first gate control signal such that the first power disconnect switch turns on before the second power disconnect switch when powering up a load coupled to the first and the second power disconnect switches. The gate driver circuit logic may also be configured to implement a delayed turn off time such that the first power disconnect switch turns off before the second power disconnect switch when powering down the load. Corresponding power conversion circuits, electronic systems, and methods of power disconnect switch control are also described.

A power conversion device includes two lower arm switching elements connected in parallel to each other and a lower arm driver circuit that drives the two lower arm switching elements. The two lower arm switching elements respectively include gate terminals and detection terminals used to detect counter-electromotive forces. The power conversion device includes a common connection line that connects the two detection terminals to each other and connects the two detection terminals to an addition circuit of the lower arm driver circuit. A combined electromotive force is transmitted via the common connection line.

Electronic circuits are disclosed. One electronic circuit includes: a transistor device having a load path and a drive input; a first drive circuit configured to receive a supply voltage and generate a drive signal for the transistor device based on the supply voltage; and a biasing circuit connected in parallel with the load path of the transistor device. The biasing circuit includes a bias voltage circuit configured to receive the supply voltage and generate a bias voltage higher than the supply voltage based on the supply voltage.

Electronic circuits are disclosed. One electronic circuit includes: a transistor device having a load path and a drive input; a first drive circuit configured to receive a supply voltage and generate a drive signal for the transistor device based on the supply voltage; and a biasing circuit connected in parallel with the load path of the transistor device. The biasing circuit includes a bias voltage circuit configured to receive the supply voltage and generate a bias voltage higher than the supply voltage based on the supply voltage.

An adjuster includes a power transfer circuit, a negative feedback circuit, a constant current source circuit and a control circuit. Two inputs of an error amplifier in the negative feedback circuit receive a reference voltage and a feedback voltage corresponding to an output signal of the adjuster respectively, and the error amplifier is configured to output a first voltage signal when the feedback voltage is less than the reference voltage, and output a second voltage signal when the feedback voltage is greater than the reference voltage, during the starting process of the adjuster. The control circuit is configured to control the negative feedback circuit to be turned off and the constant current source circuit to be turned on, and control the constant current source circuit to be turned off and the negative circuit to be turned on according to the second voltage signal.

Electronic circuits are disclosed. One electronic circuit includes: a transistor device having a load path and a drive input; a first drive circuit configured to receive a supply voltage and generate a drive signal for the transistor device based on the supply voltage; and a biasing circuit connected in parallel with the load path of the transistor device. The biasing circuit includes a bias voltage circuit configured to receive the supply voltage and generate a bias voltage higher than the supply voltage based on the supply voltage.